JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

Course Objectives:

• 1. To know the IR drop, Power requirements, power mesh design, and electro migration.
• 2. To know the design of power optimization techniques.
• 3. To understand the On-chip variations and their impact on performance of design.
• 4. To know Foundry design rules and implementation methodologies.

Course Outcomes

Student will be able to:

• 1. Design power mesh for given specifications, analyze IR drop and EM issues and fix them.
• 2. Implement the low power intent of the design using current industry standard UPF.
• 3. Verify whether the design meets the power intent in UPF
• 4. Perform physical verification both at LVS & DRC level and fix all issues.

UNIT - I

Power Analysis: Introduction to power analysis, Goals and objectives, Data preparation, Power mesh design, Static IR analysis, Dynamic IR analysis, Signal and power EM.

UNIT - II

Low Power Design – I: Introduction, Low power optimization in the SOC flow, Special cells for power management, Architectural techniques for low power.

UNIT - III

Low Power Design – II: Low power implementation techniques (multi voltage, power gating etc.), UPF formats, Low power checks.

UNIT - IV

Advanced STA: Hierarchical STA (ILM, XILM, ETM), On-chip variations, Advanced on-chip variations, Parametric on chip variations, Introduction to LVF.

UNIT - V

Physical Verification: Physical verification - Introduction, goals and objectives, design rule check, layout versus schematic check and electrical rule check, Design for manufacturability - Introduction, DFM aware routing, DFM checks and fixing (pattern matching, MAS).

TEXT BOOK:

• 1. Rakesh Chadha and J. Bhasker, "An ASIC Low Power Primer", Springer, 2013.

REFERENCE BOOKS:

• 1. Voltus Reference Manuals, 17.12.000.
• 2. Tempus Reference Manual, 17.12.000.
• 3. Calibre Reference Manual, 2017.1_17.12 M.TECH.- I YEAR- II SEMESTER VLSI/VLSI DESIGN/VLSI SYSTEM DESIGN