JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II COMPUTER ORGANIZATION Previous Question Paper (July/August - 2021 - R16)

A microprogram sequencer is a functional unit that determines the address of the next microinstruction to be executed in the control memory. It generates the address based on the current microinstruction, status flags, and external inputs, ensuring the correct sequence of control signals is generated for the processor.

The block diagram of a microprogram sequencer typically consists of the following components:

• Multiplexer (MUX): Selects the next address from various sources: the incremented address, a branch address from the microinstruction, or an address from the stack.
• Control Address Register (CAR): Holds the address of the microinstruction currently being read from the control memory.
• Incrementer: Increments the CAR value to point to the next sequential microinstruction.
• Subroutine Register/Stack: Stores return addresses when a micro-subroutine is called.
• Status Bits: External inputs (like zero, carry, or sign flags) that influence conditional branching.

Operational Details:

• Sequential Execution: The sequencer normally increments the CAR by 1 to fetch the next instruction in the control store.
• Conditional Branching: The sequencer uses status bits to test conditions. If a condition is met, the MUX selects the branch address provided by the microinstruction field.
• Subroutine Calls: When a micro-subroutine is invoked, the current incremented address is pushed onto the stack, and the CAR is loaded with the subroutine's entry point.
• Return from Subroutine: Upon completing the subroutine, the address stored at the top of the stack is popped back into the CAR to resume execution from the calling point.

By managing these transitions, the microprogram sequencer acts as the 'program counter' for the control unit, effectively controlling the flow of micro-operations that execute machine-level instructions.

To manage the memory and instruction architecture described, we must first analyze the memory organization and instruction format:

• Memory Capacity: 16,384 words = 2¹⁴ words. This requires a 14-bit address bus to address each unique memory location.
• Word Size: 40 bits per word.
• Instruction Format: Each instruction consists of 6 bits (Opcode) + 14 bits (Address) = 20 bits total.
• Packing: Since each word is 40 bits and each instruction is 20 bits, exactly two instructions fit into a single memory word.

The instruction execution procedure is governed by the Program Counter (PC), which must be able to track both the memory word address and the specific instruction half (left or right) within that word. A 15-bit PC is required: 14 bits for the memory address and 1 bit to indicate the instruction half (0 for the first 20 bits, 1 for the second 20 bits).

The fetch and execute cycle follows these steps:

1. Fetch Phase:
   The control unit places the 14-bit address from the PC onto the address bus. The memory unit reads the 40-bit word into the Memory Buffer Register (MBR).
2. Instruction Selection:
   Based on the 15th bit of the PC, the control unit selects either the upper 20 bits or the lower 20 bits of the MBR and transfers them into the Instruction Register (IR).
3. PC Update:
   The PC is incremented. If the current instruction was the first half (bit 14=0), the PC bit 14 is toggled to 1. If it was the second half (bit 14=1), the 14-bit address portion is incremented by 1 and the 15th bit is reset to 0.
4. Decode Phase:
   The 6-bit opcode in the IR is sent to the Instruction Decoder to determine the required control signals for the operation.
5. Effective Address Calculation:
   The 14-bit address field of the IR is used to access the operand memory location if the instruction requires memory reference.
6. Execution Phase:
   The control unit generates the sequence of micro-operations corresponding to the decoded opcode. The Arithmetic Logic Unit (ALU) performs the necessary data manipulation, and the result is stored in the Accumulator (AC) or the specified memory location.

This procedure ensures that the 40-bit word capacity is fully utilized by treating the 15th bit of the PC as a pointer to the specific 20-bit instruction segment within the word.