Jawaharlal Nehru Technological University Hyderabad B.Tech III ADVANCED COMPUTER ARCHITECTURE Previous Question Paper (August - 2022 - R18)

Shared-memory multiprocessors allow multiple processors to access a common global address space. The primary models are classified based on how memory is organized and accessed:

1. Uniform Memory Access (UMA): All processors share a single centralized memory unit. The access time to any memory location is identical for all processors. This model is typically implemented using a bus or crossbar switch and is suitable for small-scale systems.
2. Non-Uniform Memory Access (NUMA): Memory is physically distributed among processors, but it remains logically shared. Accessing local memory is faster than accessing remote memory located at another processor's node. This model scales well to large systems.
3. Cache-Only Memory Architecture (COMA): A specialized form of NUMA where the main memory at each node acts as a large cache. Data migrates dynamically to the node where it is currently being accessed, eliminating the need for static memory allocation.

The development of parallel computers follows a hierarchical structure where each layer abstracts the complexity of the one below it, facilitating design and programming:

1. Application Layer: The top layer consisting of end-user programs and algorithms designed to solve specific problems using parallel processing techniques.
2. Programming Language Layer: Provides high-level constructs (e.g., OpenMP, MPI) that allow developers to express parallelism without managing low-level hardware details.
3. Compiler/Runtime Layer: Translates high-level parallel code into machine-executable instructions, managing thread scheduling, load balancing, and communication overhead.
4. Instruction Set Architecture (ISA) Layer: Defines the interface between software and hardware, specifying the set of instructions the processors can execute.
5. Hardware/Architecture Layer: The physical implementation, including the processor cores, memory hierarchy, interconnection networks, and I/O devices that execute the parallel tasks.