JNTU
JNTU B.Tech II DIGITAL SYSTEM DESIGN Previous Question Paper (October - 2020 - R18)
Answer any five questions. All questions carry equal marks.
Main
Convert the following to Binary and then to gray code:
i) (AB33)16 ii) (3323)8
Answer
i) (AB33)16 to Binary: A=1010, B=1011, 3=0011, 3=0011. Binary = 1010101100110011. Gray code conversion: 1010101100110011 (Binary) → 1111110110101010 (Gray).
ii) (3323)8 to Binary: 3=011, 3=011, 2=010, 3=011. Binary = 011011010011. Gray code conversion: 011011010011 (Binary) → 010110111010 (Gray).
Perform the subtraction with the following unsigned binary numbers by taking the 2's complement of the subtrahend:
i) 11010 – 10010 ii) 100 – 110000
Answer
i) 11010 - 10010: 2's complement of 10010 is 01101 + 1 = 01110. Adding: 11010 + 01110 = 101000. Discarding the carry, the result is 01000 (8 in decimal).
ii) 100 - 110000: Pad 100 to 000100. 2's complement of 110000 is 001111 + 1 = 010000. Adding: 000100 + 010000 = 010100. Since there is no carry, the result is negative, represented by the 2's complement of 010100, which is 101011 + 1 = 101100. Result is -101100.
Derive Boolean expression for a 2 input Ex-NOR gate to realize with two input NOR gates, without using complemented variables and draw the circuit.
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Implement the function F with the following two level forms:
i) NAND-AND ii) AND-NOR
F(A,B,C,D) = Σ(0,1,2,3,4,8,9,12)
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For the given function F(A, B, C, D, E) = Σ(0,1, 2, 3, 4, 5, 9, 10, 16, 17, 18, 19, 20, 22, 25, 26) + Σd(7, 11, 12, 13, 15, 23, 27, 28, 29, 30). Obtain minimal SOP expression using K-Map.
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Implement the multiple output combinational logic circuit using a 4 line to 16 line decoder.
f1 = Σm(1, 2, 4, 7, 8, 11, 12, 13, 14, 15), f2 = Σm(0, 1, 3, 5, 8, 9, 15), f3 = Σm(2, 3, 4, 7), f4 = Σm(0, 1, 3, 4, 7, 9)
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Design a 32:1 Multiplexer using two 16:1 and 2:1 Multiplexers.
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Design a 4 bit universal shift register and draw the circuit with the given mode of operation table.
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Explain how a T Flip-Flop is converted to J-K Flip-Flop.
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Using the method of flip flop conversion carry out S-R to T conversion.
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Design and implement a MOD-7 synchronous counter using T flip-flops.
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Design a Mod-6 synchronous counter using J-K flip flops.
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Explain the design of a serial binary adder.
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Draw and explain the circuit diagram of a diode OR gate for positive logic.
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Draw the circuit diagram of diode-transistor logic NOR gate and explain its operation.
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