Jawaharlal Nehru Technological University Hyderabad
Jawaharlal Nehru Technological University Hyderabad B.Tech II Year SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (March - 2022 - R13)
Answer any five questions
All questions carry equal marks
Main
Convert the following numbers to binary: i) (7EB9)16 ii) (7654)8 iii) (525.25)10
Answer
i) To convert (7EB9)16 to binary, replace each hexadecimal digit with its 4-bit binary equivalent:
7 = 0111, E = 1110, B = 1011, 9 = 1001.
Result: 01111110101110012
ii) To convert (7654)8 to binary, replace each octal digit with its 3-bit binary equivalent:
7 = 111, 6 = 110, 5 = 101, 4 = 100.
Result: 1111101011002
iii) To convert (525.25)10 to binary, convert the integer part (525) by repeated division by 2 and the fractional part (0.25) by repeated multiplication by 2:
525 ÷ 2 = 262 R 1; 262 ÷ 2 = 131 R 0; 131 ÷ 2 = 65 R 1; 65 ÷ 2 = 32 R 1; 32 ÷ 2 = 16 R 0; 16 ÷ 2 = 8 R 0; 8 ÷ 2 = 4 R 0; 4 ÷ 2 = 2 R 0; 2 ÷ 2 = 1 R 0; 1 ÷ 2 = 0 R 1.
Integer part: 1000001101.
0.25 × 2 = 0.5 (0); 0.5 × 2 = 1.0 (1).
Fractional part: 0.01.
Result: 1000001101.012
Obtain the compliment of the following Boolean expressions: (i) A′B+A′BC′+A′BCD+A′BC′D′E. (ii) ABEF+ABE′F′+A′B′EF
Answer
To find the complement of a Boolean expression, apply De Morgan's Laws and the principle of duality.
(i) F = A'B + A'BC' + A'BCD + A'BC'D'E
First, simplify the expression: F = A'B(1 + C' + CD + C'D'E) = A'B.
The complement F' = (A'B)' = A + B'.
(ii) F = ABEF + ABE'F' + A'B'EF
Using De Morgan's Law (X + Y)' = X'Y':
F' = (ABEF)' · (ABE'F')' · (A'B'EF)'
F' = (A' + B' + E' + F') · (A' + B' + E + F) · (A + B + E' + F')
Design a 4 bit comparator circuit using logic gates.
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Perform the following using BCD arithmetic (i) (79)10 + (177)10 (ii) (481)10 + (178)10
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Simplify the following Boolean function using tabular method: f(w, x, y, z) = ∑(2, 6, 8, 9, 10, 11, 14, 15)
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Design 32:1 Mux using two 16:1 Muxs and one 2:1 Mux.
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Minimize the following Boolean function using K-Map F(A, B, C, D)= Σm(0, 2, 4, 6, 8, 10, 12, 14) and Realize it using NAND Gates.
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Implement a 2-bit Magnitude comparator and outline design procedure.
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Write the differences between combinational and sequential circuits.
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Define the following terms in connection with a flip-flop: (i) Setup time (ii) Hold time (iii) Propagation delay time (iv) Preset (v) Clear.
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Design and implement 3-bit ripple counter using J-K flip flop. Draw the state diagram, logic diagram and timing diagram for the same.
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Design a synchronous counter to generate the sequence 0, 1, 1, 2, 3, 5, 8, and repeat the sequence using T flip-flops.
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Explain in detail about the design procedures involved with designing an asynchronous sequential circuit by minimizing the circuit complexity and producing a stable circuit without critical races.
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Design control logic through ASM Chart for the sequence detector which detects 1100 and resets flip flop F to 0 and flip flop E to 1. The patterns come from 4 bit counter A.
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