JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (May/June - 2019 - R15)
Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks.
Part A
AB+A′C+BC = AB+A′C represents which theorem?
Answer
The expression AB + A'C + BC = AB + A'C represents the Consensus Theorem. In this theorem, the term BC is the consensus of the terms AB and A'C, and can therefore be eliminated from the expression.
Find the radix of the number system, if 302/20=12.1.
Answer
Let the radix of the number system be r. The given equation 302/20 = 12.1 can be expressed in base r as:
Multiplying both sides by 2r to clear the denominator:
Simplifying the equation:
Since the radix must be greater than the digits present in the number (specifically greater than 3), we discard r = 0. Therefore, the radix of the number system is 4.
How many adjacent cells are there to each cell in a n variable K-map?
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What are wired logic?
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Compare latch and flip flop.
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What are timing considerations?
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List out the drawbacks of ripple counters?
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Draw the state diagram for SR-FF.
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What are capabilities of finite state machine?
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Mention the salient features of ASM chart.
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Unit I
Write the properties of XOR gates.
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Convert (A0F9.0EB)16 to decimal, binary, octal.
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Simplify the following Boolean expressions using the Boolean theorems: (i) (A+B+C) (B′+C) + (A+D) (A′+C) (ii) (A+B) (A+B′) (A′+B)
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Why a NAND and NOR gates are known as universal gates? Simulate all the Gates.
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Unit II
Minimize the following expressions using K-map and realize using NAND Gates: f = ∑ m (1,3,5,8,9,11,15) +d (2,13)
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Minimize the following expression using K-map and realize using NOR Gates: f = ∏ M (1,2,3,8,9,10,11,15) . d (7,1,5)
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Explain the differences between a MUX and a DEMUX. Realize 16-input multiplexer by cascading of two 8-input multiplexers 74151.
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Realize the function f(A,B,C,D) = ∏(1,4,6,10,14) + d (0,8,11,15) using (i) 16:1 MUX (ii) 8:1 MUX.
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Unit III
Explain the operation of R-S master slave flip flop. Explain its truth table.
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Explain about the realization of SR flip-flop, JK flip-flop using D flip-flop.
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Realize D-FF and T-FF using JK-FF. Draw the logic diagrams with their truth tables.
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Deduce the design procedure for sequential logic circuits and give the classification of sequential logic circuits.
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Unit IV
Design, draw and explain a synchronous MOD-12 down-counter using J-K flip-flop.
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Design, draw and explain a 4-bit ring counter using D- flip flops with relevant timing diagrams.
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Explain the differences between asynchronous and synchronous counters. Design a MOD-10 ripple counter.
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Design and construct MOD-5 synchronous counter using JK flip flops.
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Unit V
Compare Mealy and Moore machines.
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Explain the procedure for state minimization using merger graph and merger table with example.
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Differentiate between an ASM chart and a conventional flow chart.
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Explain in detail the ASM technique of designing a sequential circuit.
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