JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B. Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (April/May - 2023 - R13)
Note: i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
Part A
Define Concurrency.
Answer
Concurrency in Verilog HDL refers to the execution of multiple statements or blocks of code simultaneously. Unlike software programming languages that execute statements sequentially, Verilog models hardware behavior where all always and initial blocks, as well as continuous assignments, act in parallel to represent the concurrent nature of physical electronic circuits.
What are the different categories of System function that add flexibility to the flexibility of test benches?
Answer
System functions in Verilog provide essential capabilities for test bench development, primarily categorized into the following types:
- Simulation Control Functions: These functions manage the execution flow of the simulation, such as
$finishto terminate the simulation and$stopto suspend it for debugging. - Display and Formatting Functions: These functions allow for monitoring and reporting data during simulation, including
$display,$write,$monitor, and$strobe, which are critical for verifying output signals. - File I/O Functions: These functions enable reading from and writing to external files, such as
$fopen,$fclose, and$fdisplay, which are used for logging test results or reading stimulus vectors. - Time and Mathematical Functions: Functions like
$timeand$realtimeprovide current simulation time, while mathematical functions like$powor$sqrtassist in complex data verification.
What are the basic rules for Operator Precedence for the sequence of execution?
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What are the factors that decide the bit-width of the result when expressions are evaluated?
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What is meant by Initial Construct?
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Illustrate the structure of ‘repeat’ block.
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How Propagation delays can be specified for switch primitives on the same line as was done with gate primitives?
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What is the use of Compiler Directives?
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What are the Basic Memory Components used in the Sequential Circuit Design?
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What are the different Test Bench Techniques?
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Part B
Describe the structure of a typical Simulation Module with an example.
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What are the data types available in Verilog HDL? Discuss them with necessary syntax and an example.
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Explain how the components of Target design can be described at different levels with the help of the constructs in Verilog.
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Discuss the concept of numbers in language constructs.
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What is a three-state gate and explain each type of three-state gate with truth tables?
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Write the Module and test bench for the AOI gate shown in figure below.
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Write the module and test bench for a Ring Counter.
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Prepare a 2-bit ALU module and its test bench. Let the module inputs-A and B be 2-bit wide. Ci is carry input and Co is carry output whereas D is the 2-bit output. F is the function selection vector. If F=1, D=A+B; if F=2, D=A + B + Ci; if F=3, D=A-B; if F=4, D=A-B-Ci; if F=5, D = A OR B; if F=6, D=A AND B; if F = 7, D = A XOR B.
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Describe the characterization of Procedural Assignment used for the Design Description at the Behavioral Level.
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Explain blocking and Non-blocking statements with examples.
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Design a counter module and test bench to illustrate the use of WAIT.
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Illustrate the syntax for the following constructs and give examples (i) Always ii) if, if-else.
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Build a dynamic 2-to-4 NOR gate-based decoder and a dynamic 2-to-4 NAND gate-based decoder using NMOS switches and PMOS switches.
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Discuss about the wide range of time scales as well as precision levels that are available for selection during simulation with an example.
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Implement a 4-bit look-ahead adder using CMOS logic and test it with a test bench.
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Briefly outline the features of Display Tasks with an example.
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Explain in detail about Assertion Verification of a system.
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Briefly explain about the Capacitive Model with an example.
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Briefly explain any one method used for combinational circuit testing.
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Discuss in detail about Sequential Synthesis with an example.
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