JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (December - 2017 - R13)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.
Part A
Explain about strobe tasks.
Answer
Strobe tasks in Verilog are user-defined tasks that are executed at a specific point in simulation time, typically used for debugging and monitoring. They are invoked using a task call and can be used to display messages, check signal values, or perform other actions without affecting the design's functionality. A common use is to check for race conditions or unexpected behavior during simulation.
Define logic levels relevant to verilog HDL.
Answer
Verilog HDL defines four primary logic levels:
- 0: Represents a logic low or false state.
- 1: Represents a logic high or true state.
- X: Represents an unknown or uninitialized logic state. This occurs when a signal's value cannot be determined, such as during simulation startup or due to contention.
- Z: Represents a high-impedance state. This occurs when a tri-state buffer is disabled or when multiple drivers are connected to a net without proper control.
What is drive strength of a device or gate in verilog.
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Explain NOR gate primitive with example.
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Define fork-join block.
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Define force-release construct with an example.
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Design verilog module for 4-bit full adder using dataflow operators.
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What is recursive function
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Write a short note on design verification.
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Explain about implicit model.
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Part B
Explain the synthesis procedure in verilog HDL.
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Classify the data types and explain.
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Explain different levels of design description in verilog.
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What are the functions of programming language interface (PLI)? Explain.
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Write notes on tristate gates. Give the relevant syntax, logic diagrams and excitation tables.
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Discuss about strings in detail.
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Explain continous assignment structures with examples.
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Write about net delay with an example.
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Design verilog module to identify the highest priority interrupts.
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Write test bench simulation results of above question with explanation.
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Write the differences between begin-end and fork-join blocks.
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Explain about multiple always blocks.
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What do you mean by user defined primitive? Explain the types with examples.
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Explain briefly the module paths.
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Discuss the basic transistor switches.
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Explain the computer directives.
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Write and explain the verilog module for positive edge trigger flip-flop.
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Discuss setup hold, width and period checks used in verilog.
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Explain cross coupled NOR latch.
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What are the various sequential memory storage models explain in detail.
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