JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (December - 2017 - R15)

Explain about strobe tasks.

Define logic levels relevant to verilog HDL.

What is drive strength of a device or gate in verilog.

Explain NOR gate primitive with example.

Define fork-join block.

Define force-release construct with an example.

Design verilog module for 4-bit full adder using dataflow operators.

What is recursive function

Write a short note on design verification.

Explain about implicit model.

Explain the synthesis procedure in verilog HDL.

Classify the data types and explain.

Explain different levels of design description in verilog.

What are the functions of programming language interface (PLI)? Explain.

Write notes on tristate gates. Give the relevant syntax, logic diagrams and excitation tables.

Discuss about strings in detail.

Explain continous assignment structures with examples.

Write about net delay with an example.

Design verilog module to identify the highest priority interrupts.

Write test bench simulation results of above question with explanation.

Write the differences between begin-end and fork-join blocks.

Explain about multiple always blocks.

What do you mean by user defined primitive? Explain the types with examples.

Explain briefly the module paths.

Discuss the basic transistor switches.

Explain the computer directives.

Write and explain the verilog module for positive edge trigger flip-flop.

Discuss setup hold, width and period checks used in verilog.

Explain cross coupled NOR latch.

What are the various sequential memory storage models explain in detail.