JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II Year DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (December - 2018 - R13)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.
Part A
(25 Marks)
Define concurrency.
Answer
Concurrency refers to the execution of multiple statements or processes simultaneously within a hardware description language. In Verilog, this means that all procedural blocks (such as always and initial blocks) and continuous assignments operate in parallel, reflecting the inherent parallel nature of digital hardware circuits.
Explain about identifiers.
Answer
In Verilog HDL, identifiers are user-defined names assigned to objects such as modules, variables, signals, tasks, and functions. They serve as unique labels to reference these elements within the code.
The rules for defining identifiers are as follows:
- They can contain letters (a-z, A-Z), digits (0-9), the underscore character (_), and the dollar sign ($).
- The first character of an identifier must be a letter or an underscore; it cannot be a digit or a dollar sign.
- Identifiers are case-sensitive, meaning Data_Bus and data_bus are treated as distinct names.
- They cannot be a Verilog reserved keyword.
- While there is no explicit limit on length, identifiers should be kept concise and descriptive to improve code readability.
Discuss about latch.
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Explain in brief the built-in primitive gates in verilog HDL.
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Give the syntax of event construct.
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Give the syntax of disable construct.
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Define $finish task.
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What is the purpose of using system tasks and functions in verilog HDL?
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What is the function of assert_always monitor.
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Write a test bench for moore detector for synchronized data input.
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Part B
(50 Marks)
Explain about: i) Scalars and vectors ii) Operators
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List the functions performed by test bench and explain.
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Explain about the Language Interface in verilogs.
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Explain port declaration with an example using verilog code.
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Discuss about the AND Gate primitive.
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By talking one example, explain gate level modeling.
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Design a 4 bit full adder using gate level primitives.
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Explain the concurrent statements in data flow level give one example to each one.
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What are operations and assignments in behavioural modeling?
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Describe the functional bifurcation in behavioural modeling.
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Design 3-to-8 decoder and write a verilog code using ‘If-Else’ construct.
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Design 3-to-8 decoder and write a verilog code using ‘Case’ statement.
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Briefly explain the bidirectional Gates.
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Define and explain CMOS Switches.
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With examples explain instantiation with ‘strengths’ and ‘Delays’.
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Write about the Static machine coding.
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Write a verilog module for PLA.
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Explain type declaration for parameters.
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Define and explain the file based tasks and functions.
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