JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II Year DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (December - 2018 - R13)

B.Tech | II Year | II Semester | R13 | December - 2018

Answer PaperPaper Code: 114AFMaximum Marks: 75Time: 3 Hours

Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.

Part A

(25 Marks)

1a

Define concurrency.

2 marks

Answer

Concurrency refers to the execution of multiple statements or processes simultaneously within a hardware description language. In Verilog, this means that all procedural blocks (such as always and initial blocks) and continuous assignments operate in parallel, reflecting the inherent parallel nature of digital hardware circuits.

1b

Explain about identifiers.

3 marks

Answer

In Verilog HDL, identifiers are user-defined names assigned to objects such as modules, variables, signals, tasks, and functions. They serve as unique labels to reference these elements within the code.

The rules for defining identifiers are as follows:

  • They can contain letters (a-z, A-Z), digits (0-9), the underscore character (_), and the dollar sign ($).
  • The first character of an identifier must be a letter or an underscore; it cannot be a digit or a dollar sign.
  • Identifiers are case-sensitive, meaning Data_Bus and data_bus are treated as distinct names.
  • They cannot be a Verilog reserved keyword.
  • While there is no explicit limit on length, identifiers should be kept concise and descriptive to improve code readability.
1c

Discuss about latch.

2 marks

Answer

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1d

Explain in brief the built-in primitive gates in verilog HDL.

3 marks

Answer

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1e

Give the syntax of event construct.

2 marks

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1f

Give the syntax of disable construct.

3 marks

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1g

Define $finish task.

2 marks

Answer

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1h

What is the purpose of using system tasks and functions in verilog HDL?

3 marks

Answer

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1i

What is the function of assert_always monitor.

2 marks

Answer

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1j

Write a test bench for moore detector for synchronized data input.

3 marks

Answer

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Part B

(50 Marks)

210 marks
a

Explain about: i) Scalars and vectors ii) Operators

5 marks

Answer

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b

List the functions performed by test bench and explain.

5 marks

Answer

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OR
310 marks
a

Explain about the Language Interface in verilogs.

5 marks

Answer

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b

Explain port declaration with an example using verilog code.

5 marks

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410 marks
a

Discuss about the AND Gate primitive.

5 marks

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b

By talking one example, explain gate level modeling.

5 marks

Answer

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OR
510 marks
a

Design a 4 bit full adder using gate level primitives.

5 marks

Answer

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b

Explain the concurrent statements in data flow level give one example to each one.

5 marks

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610 marks
a

What are operations and assignments in behavioural modeling?

5 marks

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b

Describe the functional bifurcation in behavioural modeling.

5 marks

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OR
710 marks
a

Design 3-to-8 decoder and write a verilog code using ‘If-Else’ construct.

5 marks

Answer

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b

Design 3-to-8 decoder and write a verilog code using ‘Case’ statement.

5 marks

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810 marks
a

Briefly explain the bidirectional Gates.

5 marks

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b

Define and explain CMOS Switches.

5 marks

Answer

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OR
9

With examples explain instantiation with ‘strengths’ and ‘Delays’.

10 marks

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1010 marks
a

Write about the Static machine coding.

5 marks

Answer

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b

Write a verilog module for PLA.

5 marks

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OR
1110 marks
a

Explain type declaration for parameters.

5 marks

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b

Define and explain the file based tasks and functions.

5 marks

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About this paper

This page contains the solved question paper with answers of DIGITAL DESIGN USING VERILOG HDL from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech ECE II Year II Semester, December - 2018, R13.

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