JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (December - 2018 - R15)

Define concurrency.

Explain about identifiers.

Discuss about latch.

Explain in brief the built-in primitive gates in verilog HDL.

Give the syntax of event construct.

Give the syntax of disable construct.

Define $finish task.

What is the purpose of using system tasks and functions in verilog HDL?

What is the function of assert_always monitor.

Write a test bench for moore detector for synchronized data input.

Explain about following terms: i) Scalars and vectors ii) Operators

List the functions performed by test bench and explain

Explain about the Language Interface in verilogs.

Explain port declaration with an example using verilog code.

Discuss about the AND Gate primitive.

By talking one example, explain gate level modeling.

Design a 4 bit full adder using gate level primitives.

Explain the concurrent statements in data flow level give one example to each one.

What are operations and assignments in behavioural modeling?

Describe the functional bifurcation in behavioural modeling.

Design 3-to-8 decoder and write a verilog code using ‘If-Else’ construct.

Design 3-to-8 decoder and write a verilog code using ‘Case’ statement.

Briefly explain the bidirectional Gates.

Define and explain CMOS Switches.

Write about the Static machine coding.

Write a verilog module for PLA.

Explain type declaration for parameters.

Define and explain the file based tasks and functions.