JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (February - 2024 - R15)

What are system tasks in Verilog?

Briefly describe the difference between simulation and synthesis in Verilog.

Define the basic function of an AND gate primitive.

How can gate primitives be utilized in the design of flip-flops?

Define functional bifurcation and its role in behavioral models.

Differentiate between operations and assignments in the context of Behavioral Modeling.

What are module parameters in Verilog?

What is the role of parameters in system tasks and functions?

Briefly explain capacitive model.

Write Verilog code using Case statement.

Explain in detail about the unary, binary and ternary operators in Verilog with examples.

Describe about white space characters and variables in Verilog HDL.

Explain the role of operators in Verilog HDL. Discuss various types of operators, their precedence, and how they are utilized in the manipulation of data in Verilog code.

Explore the concept of parameters in Verilog HDL. Discuss their significance in design parameterization, configuration management.

Write Verilog module for a positive edge triggered flip flop with test bench.

What are tri-state devices? Write a Verilog code for tri-state devices.

With an example explain in detail about the use of gate primitives in the design of complex digital circuits.

Describe the role of flip-flops in sequential logic circuits and their significance in digital systems.

Explain the functionality and purpose of the 'wait' construct in behavioral modeling.

Explain the concept of multiple 'always' blocks in behavioral modeling.

Explain in detail about the functionality and syntax of the 'case' statement in behavioral modeling.

Describe the simulation flow when using 'if' and 'if-else' constructs in behavioral modeling.

Explain the concept of instantiation in Verilog? Discuss how instantiation parameters influence the behavior and performance of instantiated components.

Explain the concept of hierarchical access in Verilog and discuss its importance in organizing and managing complex designs.

Explain the concept of the implicit model in sequential circuits. Discuss how it differs from other sequential models.

Briefly explain any one method used for sequential circuit testing.

Explain in detail about formal verification of a system.

Describe the techniques employed in creating an effective test bench for sequential circuit testing.