JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (March - 2022 - R13)

Port declarations define the interface of a module, specifying the direction of data flow between the module and its environment. There are three primary port types: input, output, and inout.

The input port is a receiver of data, output is a driver of data, and inout represents a bidirectional port. In Verilog, ports must be declared within the module header or the body, and their data types (wire or reg) must be consistent with their usage.

Example:

module full_adder(input a, input b, input cin, output sum, output cout);
  assign sum = a ^ b ^ cin;
  assign cout = (a & b) | (b & cin) | (a & cin);
endmodule

White space characters, including spaces, tabs, and newlines, are used to separate tokens in Verilog. They are ignored by the compiler except when they appear within strings. They are essential for code readability and formatting.

Variables in Verilog are used to store and manipulate data. The two primary types are nets and registers:

1. Nets: Represent physical connections between components. They do not store values and must be continuously driven. The most common type is wire. Example: wire [7:0] data_bus;
2. Registers: Represent data storage elements. Unlike physical hardware registers, they hold their value until the next assignment. They are declared using the reg keyword. Example: reg [3:0] counter;

Variables can be declared as scalars (single bit) or vectors (multiple bits), as shown in the examples above.