JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (May - 2019 - R13)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks.
Part A
What is concurrency?
Answer
Concurrency refers to the ability of a system to execute multiple processes or statements simultaneously. In the context of Verilog HDL, it describes the parallel nature of hardware where all procedural blocks, continuous assignments, and module instantiations operate concurrently rather than sequentially as in software programming languages.
What are the white space characters?
Answer
In Verilog HDL, white space characters are used to separate tokens and improve code readability. They are ignored by the compiler during the lexical analysis phase. The recognized white space characters are:
- Spaces
- Tabs (horizontal and vertical)
- Newlines
- Form feeds
These characters are treated as delimiters and are not part of the actual design logic, except when they appear within string literals, where they are preserved as part of the data.
Describe array of instances of primitives.
Answer
Sign in to view the complete answer paper.
Why net delay is needed.
Answer
Sign in to view the complete answer paper.
How is procedure assignment characterized?
Answer
Sign in to view the complete answer paper.
How if and if – else constructs?
Answer
Sign in to view the complete answer paper.
What are bidirectional gates?
Answer
Sign in to view the complete answer paper.
What is mean by module paths?
Answer
Sign in to view the complete answer paper.
What are advantages and limitations feedback model of sequential circuit.
Answer
Sign in to view the complete answer paper.
How combinational circuit can be tested?
Answer
Sign in to view the complete answer paper.
Part B
What are the different models of verilog HDL programming explain them with suitable examples.
Answer
Sign in to view the complete answer paper.
Explain identifiers, comments and strings in verilog.
Answer
Sign in to view the complete answer paper.
Give details of strengths in Verilog.
Answer
Sign in to view the complete answer paper.
Prepare a full – adder module using half – adder module and OR gate primitive in verilog.
Answer
Sign in to view the complete answer paper.
Prepare a module to add 2 BCD numbers in verilog HDL.
Answer
Sign in to view the complete answer paper.
Design a J-K Flip-Flop using NAND gates. Write verilog module for this.
Answer
Sign in to view the complete answer paper.
How to introduce delays in verilog HDL programming? Why these are needed.
Answer
Sign in to view the complete answer paper.
Explain functional bifurcation with example.
Answer
Sign in to view the complete answer paper.
Prepare design module for the following operation and also prepare a suitable test bench and test the design module 2 decimal numbers each of two digits.
Answer
Sign in to view the complete answer paper.
Compare blocking and non-blocking Assignments.
Answer
Sign in to view the complete answer paper.
Prepare design module for the following operation. Prepare a suitable test bench and test the design module. Interrupt service routine (ISR) : An ISR receives an interrupt request (IRQ). The PC content is saved on a stack – 4 bytes deep. Then a specific byte 5a5ah is loaded into the PC. The ISR sets an INTA flag high and returns. Use the ‘wait’ construct and design the module.
Answer
Sign in to view the complete answer paper.
Explain strength contention with trireg nets.
Answer
Sign in to view the complete answer paper.
Implement NAND, AND, OR gates using MOS switches ; test it with a suitable test – bench.
Answer
Sign in to view the complete answer paper.
Implement a pseudo – NMOS 4 – input NOR logic gate. Write a test – bench and test it.
Answer
Sign in to view the complete answer paper.
What are the user defind primitives and write any program using these.
Answer
Sign in to view the complete answer paper.
Explain capacitive model of a sequential circuit and compare it with other models.
Answer
Sign in to view the complete answer paper.
What are the basic differences between sequential circuit testing and combinational circuit testing?
Answer
Sign in to view the complete answer paper.
What is test bench? Why it is needed.
Answer
Sign in to view the complete answer paper.