JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (November/December - 2020 - R15)

In Verilog, concurrency refers to the ability of the hardware description language to model multiple physical components operating simultaneously. Unlike procedural programming languages that execute statements sequentially, Verilog uses concurrent execution blocks such as always and initial blocks, along with continuous assignment statements. These blocks run in parallel, accurately reflecting the behavior of digital circuits where signals propagate through gates and logic paths at the same time.

Functional verification is the process of confirming that a design implementation correctly performs the intended logic functions as specified in the requirements. It involves creating a testbench to apply various input stimuli to the design under test (DUT) and comparing the observed outputs against expected results. This stage is critical in the design flow to identify and fix logical errors, timing issues, or race conditions before the design is committed to physical hardware or FPGA implementation.