JNTU
JNTU B.Tech II DIGITAL DESIGN USING VERILOG HDL Previous Question Paper (September/October - 2023 - R13)
Note: i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
PART - A
Write about system tasks.
Answer
System tasks in Verilog HDL are built-in functions used to perform specific operations during simulation, such as displaying data, monitoring signals, or controlling the simulation process. They are identified by a leading dollar sign ($) and are not synthesizable, meaning they are intended solely for testbench development and debugging purposes.
Common examples include $display for printing formatted text to the console, $monitor for tracking signal changes, and $finish to terminate the simulation.
Define scalars and vectors.
Answer
In Verilog HDL, scalars and vectors are used to define the width of nets and variables. A scalar represents a single-bit element, such as a wire or reg declared without a range specification, which can only hold a value of 0, 1, x, or z. A vector represents a multi-bit element, declared with a range specification [msb:lsb], allowing it to store a group of bits that can be accessed as a whole or as individual bits (bit-select) or segments (part-select).
Define tri-gate state.
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What is continuous assignment structure?
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Write about Repeat construct.
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Draw a simulation flow chart.
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Write about Bi Directional Gates.
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Mention the significance of module parameters.
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What is feedback model?
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Write a short note on design verification.
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PART - B
What are the different levels of design description? Explain.
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What are the functions of Programming Language Interface (PLI)? Explain.
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Explain in detail about the concepts of numbers and strings with suitable examples.
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Write a Verilog program in gate level for 3 to 8 decoder.
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Write about array of instances of primitives.
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Write a Verilog module for J K flip-flop using NAND gates.
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Write a short notes on strengths and construction.
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Design a counter module and test bench to illustrate the use of WAIT.
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Differentiate between a sequential block and a parallel block.
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Write a Verilog code using case statement for any one example.
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What is the difference between an Intra statement delay and an Inter statement delay? Explain.
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Write the code for CMOS switch of parallel combination.
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Discuss the basic transistor switches.
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Explain the different types of user defined primitives with examples.
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Write short notes on the computer directives.
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Explain capacitive model of a sequential circuit and compare it with other models.
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How the memory initialization carried out in Verilog? Explain with an example.
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Write the Verilog code for basic functional unit of a dynamic shift register.
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