JNTU
JNTU B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (April - 2018 - R16)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.
PART - A
What is self complementing code? Give example.
Answer
A code is said to be self-complementing if the 9's complement of a decimal digit can be obtained by simply complementing each bit of the corresponding code word. An example is the Excess-3 code.
State and Prove Demorgan’s theorem.
Answer
De Morgan's theorems state:
Proof for (A + B)' = A' ⋅ B': If A+B=0, then (A+B)'=1. If A=0 and B=0, then A'=1 and B'=1, so A'⋅B'=1. If A+B=1, then (A+B)'=0. If A=1 or B=1, then A'=0 or B'=0, so A'⋅B'=0. Since the truth tables match for all inputs, the theorem is proven.
What are Hazards? List their types.
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Design 2 × 1 Multiplexer with neat logic diagram.
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Write the characteristic table of JK Flip flop.
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Draw the logic diagram of Master-Slave D flip flop. Use NAND gates.
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What is switch tail ring counter?
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What is a Ring Counter? What are applications of Ring counters?
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What is an ASM Block?
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Define merger graph of n-state machine M.
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PART - B
i) Convert the given Octal number (2564. 603)8 to Hexadecimal Number. ii) Given that (81)10 = (100)b , Find the value of b.
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Encode data bits 1101 into 7 bit even parity Hamming Code.
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Prove that AB'C + B + BD'+ ABD'+ A'C = B + C.
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Simplify the following expression F = AB'+ABD+ABD'+A'C'D'+A'BC' and implement with NAND gates.
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Design a code converter that converts BCD messages into Excess-3 code. The converter has four input lines carrying signals labeled w, x, y and z and four output lines carrying signals f1, f2, f3, and f4.
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Simplify the following Boolean expression using K- map and implement them with NOR logic gates F(A,B,C,D)= Σ m ( 1,3,7,11,15 ) + d(0,2,5)
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Design and explain 3 to 8 decoder with necessary truth table and logic diagram.
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Write short notes on Hazards and Hazard free relations.
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Derive the characteristic equation for JK flip-flop and T flip-flop.
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Distinguish combinational and sequential circuits.
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What are the fundamentals of Sequential machine operation?
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Discuss about binary cell in detail.
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Design a 4-bit binary synchronous counter with D flip flops.
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What are the steps in state reduction? Explain with an example.
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Construct a Johnson counter for 10 timing signals.
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Draw the 4-bit binary ripple counter using flip flops that trigger on positive edge transition.
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Draw the Merger Graph and obtain the set of maximum compatibilities for the given incompletely specified sequential machine.
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Draw the State diagram, State table and ASM chart for a D flip-flop.
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Draw the State diagram and ASM chart for sequence detector to detect 1010.
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We wish to design a sequence detector circuit, which detects three or more consecutive 1’s in a string of bits coming through an input line. i) Find the state diagram. ii) Determine the type of the circuit (Moore or Mealy model).
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