Jawaharlal Nehru Technological University Hyderabad
Jawaharlal Nehru Technological University Hyderabad B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (July/August - 2021 - R15)
Answer any five questions. All questions carry equal marks.
Main
i) Convert the given Octal number (756.603)8 to Hexadecimal Number?
ii) Given that (16)10 = (100)b, find the value of b.
Answer
i) To convert (756.603)8 to hexadecimal, first convert the octal number to binary by representing each digit as a 3-bit group:
Binary representation: 111101110.1100000112. Now, group the binary digits into sets of four starting from the radix point:
ii) Given (16)10 = (100)b, we express the value as a polynomial expansion:
Encode data bits 1101 into 7 bit even parity Hamming Code.
Answer
For 4 data bits (d3d5d6d7 = 1101), we require 3 parity bits (p1, p2, p4) to form a 7-bit Hamming code. The bit positions are p1, p2, d3, p4, d5, d6, d7.
- Position 3: 1, Position 5: 1, Position 6: 0, Position 7: 1.
- Parity p1 (positions 1, 3, 5, 7): 1 ⊕ 1 ⊕ 1 = 1. For even parity, p1 = 1.
- Parity p2 (positions 2, 3, 6, 7): 1 ⊕ 1 ⊕ 0 ⊕ 1 = 1. For even parity, p2 = 1.
- Parity p4 (positions 4, 5, 6, 7): 1 ⊕ 1 ⊕ 0 ⊕ 1 = 1. For even parity, p4 = 1.
The resulting 7-bit even parity Hamming code is 1111101.
Prove that AB′C + B + BD′ + ABD′ + A′C = B + C
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Simplify the following expression F = AB′ + ABD + ABD′ + A′C′D′ + A′BC′ and implement with NAND gates.
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Obtain the simplified expression in SOP form and identify Prime implicants and Essential prime implicants: F(A,B,C,D) = Σm(0,1,2,3,4,8,12)
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Simplify the following Boolean expression using K-map and implement them with NOR logic gates: F(A,B,C,D) = Σm(1,3,7,11,15) + d(0,2,5)
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Design a combinational circuit with three input variables that will produce a logic ‘1’ output when more than one input variables are logic ‘1’.
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Design and explain 3 to 8 decoder with necessary truth table and logic diagram.
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Explain about Triggering methods in sequential circuits.
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Design SR flip flop using NAND gates and explain its operation.
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Convert D flip-flop to SR flip-flop.
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Derive the characteristic equation for JK flip-flop and T flip-flop.
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Design a 3-bit counter which counts the following sequence: 0 → 2 → 5 → 3 → 4 → 0 → 2
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Explain about Bi-directional Shift Register.
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Draw the State diagram and ASM chart for sequence detector to detect 1010.
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Draw the State diagram, State table and ASM chart for a D flip-flop.
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