Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III COMPUTER ORGANIZATION Previous Question Paper (February - 2022 - R16)

B.Tech | III | I | R16 | February - 2022

Answer PaperPaper Code: 135BZMaximum Marks: 75Time: 3 Hours

Answer any five questions. All questions carry equal marks.

Main

1

How the address of next instruction is generated using microprogram sequencer? Discuss with neat block diagram.

15 marks

Answer

A microprogram sequencer is a functional unit in a control unit that determines the address of the next microinstruction to be executed. It manages the flow of control within the microprogram by selecting the next address from various sources based on the current microinstruction, status flags, and external inputs.

The sequence of operations to generate the next address is as follows:

  • Incrementer: The current address in the Control Address Register (CAR) is incremented by 1 to point to the next sequential microinstruction.
  • Branch Address: A field within the current microinstruction may contain a branch address, which is loaded into the CAR if a jump condition is met.
  • Subroutine Return: A Subroutine Register (SBR) stores the return address when a micro-subroutine is called, allowing the sequencer to jump back to the main microprogram.
  • External Mapping: For initial instruction execution, an external mapping logic converts the opcode of the machine instruction into a starting microprogram address.

The block diagram consists of the following components:

  • Control Address Register (CAR): Holds the address of the microinstruction currently being read from the Control Memory.
  • Control Memory: Stores the microprograms.
  • Multiplexer: Selects the next address from the incrementer, the branch address field, the SBR, or the mapping logic based on the control signals from the instruction register and status flags.
  • Subroutine Register (SBR): Used to save the return address during a micro-subroutine call.
Next Address = f(CAR+1, Branch Address, SBR, Mapping Logic)

The sequencer uses a multiplexer controlled by the status bits and the microinstruction's branch control field to determine which of these sources will provide the next address to the CAR. This mechanism allows for conditional branching, looping, and subroutine calls within the microprogram, effectively controlling the execution of machine-level instructions.

215 marks
a

Explain the design of control unit.

7 marks

Answer

The control unit (CU) is the central component of the CPU that directs the flow of data and instructions. Its design involves generating control signals to coordinate the operations of the ALU, registers, and memory. The two primary design approaches are:

  1. Hardwired Control: Implemented using fixed logic circuits, such as gates, flip-flops, and decoders. It is extremely fast but inflexible, as changing the instruction set requires physical hardware modifications.
  2. Microprogrammed Control: Uses a control memory (ROM) to store microinstructions. A control address register (CAR) points to the next microinstruction. This approach is more flexible, allowing for complex instruction sets and easier updates through firmware, though it is generally slower than hardwired logic.

The design process typically involves identifying the required control signals for each instruction, determining the sequence of states, and implementing the logic using either a combinational circuit or a microprogram sequencer.

b

Explain the memory reference instructions.

8 marks

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3

Explain the following addressing modes with examples:

15 marks
a

Immediate addressing mode

5 marks

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b

Direct addressing mode

5 marks

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c

Indirect addressing mode.

5 marks

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415 marks
a

Explain about the general Bus operation of 8086.

9 marks

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b

Explain the machine language instruction formats.

6 marks

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515 marks
a

Write an ALP to find whether the given number is a prime number or not.

6 marks

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b

Explain about interrupt cycle of 8086.

9 marks

Answer

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615 marks
a

Write an ALP to convert decimal to hexadecimal.

7 marks

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b

Explain about interrupt service routines.

8 marks

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715 marks
a

Draw the flow chart for hardware division algorithm.

7 marks

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b

Explain about DMA.

8 marks

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815 marks
a

Explain the characteristics of multiprocessors.

6 marks

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b

What is Cache Coherence Problem? How can you overcome Cache Coherence Problem?

9 marks

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About this paper

This page contains the question paper of COMPUTER ORGANIZATION from Jawaharlal Nehru Technological University Hyderabad for B.Tech ECE III I, February - 2022, R16.

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