JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV ANALOG CMOS IC DESIGN Previous Question Paper (December - 2020 - R16)

The parasitic capacitances in a MOSFET arise from the physical structure of the device and significantly impact high-frequency performance and switching speed. These include:

• Gate Capacitances: Includes gate-to-source (Cgs), gate-to-drain (Cgd), and gate-to-bulk (Cgb). These are formed by the oxide layer between the gate electrode and the channel/substrate.
• Junction Capacitances: The depletion regions at the source-to-bulk and drain-to-bulk junctions act as reverse-biased diodes, creating voltage-dependent junction capacitances (Csb and Cdb).
• Overlap Capacitances: Formed by the physical overlap of the gate electrode with the source and drain regions due to lateral diffusion.

The small-signal model incorporates these by adding Cgs and Cgd between the gate and source/drain terminals, and Cdb and Csb between the drain/source and the bulk. The transconductance (gm) remains the primary current source, while the output resistance (ro) accounts for channel length modulation. The total gate capacitance is often modeled as Cgs + Cgd, which limits the unity-gain frequency (fT) of the transistor.

The photolithographic process involves the following sequential operations:

1. Surface Preparation: Cleaning the wafer to remove contaminants and applying an adhesion promoter.
2. Spin Coating: Applying a uniform layer of photoresist via high-speed rotation.
3. Soft Bake: Heating the wafer to evaporate solvents and harden the photoresist.
4. Alignment and Exposure: Aligning the mask and exposing the photoresist to UV light through the pattern.
5. Development: Using a developer solution to remove the exposed (positive) or unexposed (negative) photoresist.
6. Hard Bake: Final heating to solidify the remaining photoresist for subsequent etching or ion implantation.
7. Etching/Doping: Transferring the pattern into the underlying material, followed by photoresist stripping.

The transconductance g_m represents the sensitivity of the drain current I_D to changes in the gate-source voltage V_GS, defined as g_m = ∂I_D / ∂V_GS.

1. Saturation Region:
In saturation, the drain current is given by I_D = (1/2)μ_nC_ox(W/L)(V_GS - V_th)². Differentiating with respect to V_GS:

2. Linear Region:
In the linear region, the drain current is I_D = μ_nC_ox(W/L)[(V_GS - V_th)V_DS - (V_DS²/2)]. Differentiating with respect to V_GS:

Significance of Parameters:

• μ_n (Electron Mobility): Determines the speed of charge carriers in the channel; higher mobility leads to higher transconductance.
• C_ox (Gate Oxide Capacitance per unit area): Represents the gate control efficiency; higher C_ox allows for stronger inversion and better gate control over the channel.
• W/L (Aspect Ratio): The width-to-length ratio scales the current; wider devices provide more current and higher g_m.
• (V_GS - V_th) (Overdrive Voltage): In saturation, this dictates the degree of inversion; increasing the overdrive voltage increases g_m.
• V_DS (Drain-Source Voltage): In the linear region, g_m is directly proportional to V_DS, indicating that the drain voltage acts as a control parameter for the channel conductance.