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Jawaharlal Nehru Technological University Hyderabad B.Tech IV Year ANALOG CMOS IC DESIGN Previous Question Paper (September - 2022 - R16)

B.Tech | IV Year | II Semester | R16 | September - 2022

Answer PaperPaper Code: 138AQMaximum Marks: 75Time: 3 Hours

Answer any five questions. All questions carry equal marks.

Main

1

Draw the small-signal model for the MOS transistor. Briefly explain each component in that.

15 marks

Answer

The small-signal model of a MOSFET represents the device's behavior for small deviations around a stable DC operating point (bias point). It is derived by linearizing the non-linear current-voltage characteristics of the transistor.

The standard small-signal model, often referred to as the hybrid-pi model, consists of the following components:

  • Gate-Source Capacitance (Cgs): Represents the capacitance between the gate and source terminals, primarily due to the overlap capacitance and the channel charge.
  • Gate-Drain Capacitance (Cgd): Represents the overlap capacitance between the gate and drain regions.
  • Transconductance (gm): This is a voltage-controlled current source that models the dependence of the drain current on the gate-source voltage. It is defined as the change in drain current for a small change in gate-source voltage.
  • gm = ∂Id / ∂Vgs
  • Output Resistance (ro): This models the finite output impedance of the MOSFET due to channel length modulation. It represents the slope of the Id versus Vds curve in the saturation region.
  • ro = 1 / λId
  • Body Transconductance (gmb): Also known as the back-gate transconductance, it accounts for the effect of the body-source voltage on the drain current, often referred to as the body effect.
  • gmb = ηgm
  • Drain-Bulk and Source-Bulk Capacitances (Cdb, Csb): These represent the parasitic junction capacitances formed by the reverse-biased depletion regions between the drain/source diffusions and the substrate.

In a typical small-signal circuit diagram, the gate is connected to the source through Cgs and to the drain through Cgd. The current source gmVgs is placed between the drain and source, in parallel with the output resistance ro and the drain-bulk capacitance Cdb.

215 marks
a

Explain about the computer simulation models.

7 marks

Answer

Computer simulation models are mathematical representations of electronic components used by circuit simulators like SPICE to predict the behavior of integrated circuits. These models bridge the gap between physical device physics and circuit-level performance analysis.

  • Level 1 Model (Shichman-Hodges): A basic model based on the square-law theory. It is computationally efficient but lacks accuracy for short-channel effects, making it unsuitable for modern sub-micron CMOS design.
  • Level 3 Model: An empirical model that incorporates semi-empirical equations to account for short-channel effects such as velocity saturation, mobility degradation, and drain-induced barrier lowering (DIBL).
  • BSIM (Berkeley Short-channel IGFET Model): The industry standard for deep sub-micron design. These are physics-based models that use a large set of parameters to accurately describe the complex behavior of MOSFETs, including quantum mechanical effects, gate leakage, and parasitic resistances.
  • Simulation Workflow: The simulator solves a system of non-linear differential equations using numerical techniques like the Newton-Raphson method to determine node voltages and branch currents based on the provided model parameters.
b

Explain about the CMOS device modelling.

8 marks

Answer

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3

What is current mirror? Explain the general properties of current mirrors with block diagram.

15 marks

Answer

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415 marks
a

Explain the difference between cascode current mirror and Wilson current mirror.

6 marks

Answer

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b

Write short notes on current sinks and sources.

9 marks

Answer

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5

Explain the following:

15 marks
a

Differential amplifiers

7 marks

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b

Current amplifiers.

8 marks

Answer

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6

Explain the high gain amplifiers architectures.

15 marks

Answer

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715 marks
a

Explain about the design of CMOS Op-Amps.

7 marks

Answer

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b

Derive the expression for power-supply rejection ratio of two-stage op-amps.

8 marks

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815 marks
a

Differentiate the Two-stage comparator and Discrete time Comparator.

7 marks

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b

Explain about the different types of Open loop comparator.

8 marks

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