JNTU B.Tech IV LOW POWER VLSI DESIGN Previous Question Paper (September - 2022 - R18)

Power dissipation in VLSI circuits is primarily categorized into two main types: dynamic power dissipation and static power dissipation. These are further subdivided based on their physical origins.

1. Dynamic Power Dissipation: This occurs due to the switching activity of transistors and is the dominant component in CMOS circuits.

• Switching Power: Caused by the charging and discharging of load capacitances (C_L) when a gate switches states. It is given by P_switching = αCV_DD²f, where α is the activity factor, C is the load capacitance, V_DD is the supply voltage, and f is the clock frequency.
• Short-Circuit Power: Occurs during the transition period when both the NMOS and PMOS transistors are momentarily ON simultaneously, creating a direct path from V_DD to ground. This results in a short-circuit current pulse.

2. Static Power Dissipation: This occurs even when the circuit is not switching (i.e., when inputs are constant). It is primarily due to leakage currents.

• Subthreshold Leakage: Current that flows between the drain and source when the gate-to-source voltage is below the threshold voltage (V_GS < V_th). As threshold voltages are scaled down to improve performance, this component increases exponentially.
• Gate-Induced Drain Leakage (GIDL): Caused by high field effects in the gate-drain overlap region, leading to carrier injection into the substrate.
• Gate Oxide Tunneling: As gate oxide thickness (T_ox) scales down, quantum mechanical tunneling of electrons through the thin oxide layer becomes significant.
• Reverse-Biased Junction Leakage: Current flowing through the reverse-biased parasitic diodes formed between the source/drain diffusion regions and the substrate (well).

Total power dissipation is the sum of these components: P_total = P_switching + P_{short-circuit} + P_static. Minimizing these requires techniques such as voltage scaling, multi-threshold CMOS (MTCMOS), and reducing switching activity.