JNTU B.Tech IV SYSTEM ON CHIP ARCHITECTURE Previous Question Paper (July/August - 2022 - R18)

Processor architecture refers to the conceptual design and fundamental operational structure of a computer system, defining how the hardware components interact, how instructions are executed, and how data is processed. It encompasses the instruction set architecture (ISA), microarchitecture, and system design.

The primary processor architectures are:

1. Von Neumann Architecture: Uses a single shared memory and bus for both data and instructions, leading to the Von Neumann bottleneck where the CPU is limited by the speed of memory access.
2. Harvard Architecture: Features physically separate memory and pathways for instructions and data, allowing simultaneous access and improved performance.
3. RISC (Reduced Instruction Set Computer): Employs a small, highly optimized set of instructions that execute in a single clock cycle, emphasizing simple hardware and efficient pipelining.
4. CISC (Complex Instruction Set Computer): Uses a large set of complex instructions capable of performing multi-step operations in a single instruction, reducing the number of instructions per program but requiring more complex hardware.

The System-on-Chip (SoC) design approach is a highly integrated methodology focused on combining multiple functional blocks—such as processors, memory, peripherals, and analog interfaces—onto a single silicon die. The design flow typically follows these stages:

1. Specification and Architecture Design: Defining system requirements, performance targets, power constraints, and selecting appropriate IP (Intellectual Property) cores.
2. IP Selection and Integration: Utilizing pre-designed and pre-verified third-party or internal IP blocks to reduce time-to-market.
3. Functional Verification: Using simulation and emulation tools to ensure the integrated design meets the functional specifications before physical implementation.
4. Logic Synthesis and Physical Design: Converting RTL code into a gate-level netlist, followed by floorplanning, placement, and routing to map the design onto silicon.
5. Design for Test (DFT): Incorporating test structures like scan chains and BIST (Built-In Self-Test) to ensure manufacturing defects can be detected.
6. Sign-off and Fabrication: Performing final timing analysis, power analysis, and physical verification (DRC/LVS) before sending the GDSII file to the foundry for manufacturing.