JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV Year SYSTEM ON CHIP ARCHITECTURE Previous Question Paper (September - 2022 - R18)

A System-on-Chip (SoC) integrates all essential components of a computer or electronic system onto a single silicon die. The basic SoC system model consists of several key functional blocks interconnected via a high-speed on-chip bus or Network-on-Chip (NoC).

The core components include:

1. Processor Cores: One or more CPUs, DSPs, or GPUs that execute instructions and perform data processing.
2. Memory Subsystem: On-chip memory including ROM for boot code, SRAM for cache and scratchpad, and memory controllers for external DRAM.
3. Peripherals and I/O: Interfaces such as UART, SPI, I2C, USB, and Ethernet controllers that allow the SoC to communicate with the outside world.
4. Interconnect/Bus: The communication backbone (e.g., AMBA AXI, AHB) that facilitates data transfer between masters and slaves.
5. Analog and Mixed-Signal Blocks: Components like Phase-Locked Loops (PLLs) for clock generation, ADCs, and DACs.

The block diagram conceptually shows these modules connected to a central bus matrix, with the processor acting as the primary master, managing data flow between memory and peripheral interfaces to perform specific system tasks efficiently.

Memory in an SoC is critical for performance, power efficiency, and area constraints. The memory architecture is typically hierarchical to balance speed, capacity, and cost.

Key memory requirements include:

1. Memory Hierarchy: SoC designs utilize a multi-level hierarchy. Small, fast L1/L2 caches are integrated directly with the processor cores to minimize latency, while larger on-chip SRAM (scratchpad memory) is used for critical real-time data.
2. External Memory Interfaces: Since on-chip storage is limited by silicon area, SoCs must interface with high-density external memory like LPDDR4/5. The memory controller is a vital SoC component that manages refresh cycles, row/column addressing, and data integrity.
3. Non-Volatile Storage: ROM or Flash memory is required to store the bootloader, firmware, and configuration data that must persist when the device is powered off.
4. Bandwidth and Latency: High-performance applications require high-bandwidth memory access. The interconnect must support concurrent access from multiple masters (e.g., DMA engines, video processors) to prevent bottlenecks.
5. Power Management: Memory consumes significant static and dynamic power. Techniques like memory banking, power gating, and voltage scaling are essential to reduce leakage current in idle states.