JNTU
JNTU B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (April - 2018 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
(25 Marks)
Convert (378.93)10 to ( )8.
Answer
Integer part: 378 / 8 = 47 remainder 2; 47 / 8 = 5 remainder 7; 5 / 8 = 0 remainder 5. Reading remainders upwards, we get 572. Fractional part: 0.93 * 8 = 7.44 (integer 7); 0.44 * 8 = 3.52 (integer 3); 0.52 * 8 = 4.16 (integer 4). Thus, (378.93)10 = (572.734)8.
State and prove Transposition theorem.
Answer
The Transposition theorem states:
Define Prime implicant and Essential prime implicant.
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Define Magnitude Comparator.
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What is a flip flop? What are the applications of flip flops?
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Define Set-up time and hold time.
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Distinguish between synchronous counters and asynchronous counters.
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What are buffer registers? What are applications of shift registers?
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Define Mealy and Moore state machines.
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Define State box, Decision box and Conditional box.
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Part B
(50 Marks)
Subtract (3520)10 - (1205)10 using 10’s Complement.
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Generate 4 bit Gray code using Mirror image property.
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Realize basic gates AND, OR, NOT using NAND gates.
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Expand A+AB+BC in to Minterms and Maxterms.
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Obtain the simplified expression in POS form. F(A,B,C,D)= Σ m ( 5,6,7,8,9,12,13,14)
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Simplify the following Boolean expression using K- map and implement with NOR logic gates F(A,B,C,D)= Σ m ( 0,1,2,3,4,5) + d(10,11,12,13,14,15)
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Design and explain Full-Adder with necessary truth table and Logic diagram.
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Design a combinational circuits which converts 4 bit BCD Code – to – XS-3 Code.
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Design JK flip flop using NAND gates and explain its operation.
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Explain the Race around condition and also explain how to eliminate it.
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Convert T flip-flop to JK flip-flop.
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Derive the characteristic equation for SR flip-flop and D flip-flop.
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Explain about Sequential circuits, State diagram and State table with an example.
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Design a sequential circuit using two D- Flip-flops with A,B and input X : if X=0, the state of the circuit remains same and if X=1 the state transitions from 00 to 01 to 11 to 10 and back to 00 and continue.
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Design Mod-6 Asynchronous Counter using T Flip-flops.
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Explain about Parallel–in, Serial-out Shift Register.
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Find the Reduced state table for the given state machine using Partition technique.
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Obtain the set of maximum compatibilities for the given sequential machine using Merger Table method.
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What are the Salient features of ASM chart?
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Draw the State diagram and ASM chart for mod-6 counter.
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