JNTU
JNTU B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (May - 2019 - R13)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit.
PART- A
What is a Parity bit? What do you mean by even parity and odd parity?
Answer
A parity bit is an extra bit appended to a binary string to ensure that the total number of 1s in the resulting code word is either even or odd, serving as a simple method for error detection.
Even parity means the parity bit is chosen such that the total count of 1s in the data including the parity bit is an even number. Odd parity means the parity bit is chosen such that the total count of 1s in the data including the parity bit is an odd number.
State and Prove Demorgan’s theorem.
Answer
De Morgan's theorems are two fundamental laws in Boolean algebra used to simplify logic expressions. They state:
- The complement of a product of variables is equal to the sum of their individual complements: (A ⋅ B)' = A' + B'
- The complement of a sum of variables is equal to the product of their individual complements: (A + B)' = A' ⋅ B'
To prove the first theorem, (A ⋅ B)' = A' + B', we use a truth table:
| A | B | A ⋅ B | (A ⋅ B)' | A' | B' | A' + B' |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 |
Since the columns for (A ⋅ B)' and A' + B' are identical for all possible input combinations, the theorem is proven. The second theorem can be proven similarly by comparing the truth table columns for (A + B)' and A' ⋅ B'.
Define Selective prime implicant and Redundant prime implicant.
Answer
Sign in to view the complete answer paper.
Design 2 × 1 Multiplexer with neat logic diagram.
Answer
Sign in to view the complete answer paper.
Define Clock Skew.
Answer
Sign in to view the complete answer paper.
Distinguish between combinational circuits and sequential circuits.
Answer
Sign in to view the complete answer paper.
What is a Serial-in and Parallel-out shift register?
Answer
Sign in to view the complete answer paper.
What is a Ring Counter? What are applications of Ring counters?
Answer
Sign in to view the complete answer paper.
What is an ASM chart?
Answer
Sign in to view the complete answer paper.
What are the capabilities and limitations of finite state machine?
Answer
Sign in to view the complete answer paper.
PART- B
i) Convert the given Octal number (756. 603)8 to Hexadecimal Number? ii) Given that (16)10 = (100)b , Find the value of b.
Answer
Sign in to view the complete answer paper.
Encode data bits 1101 into 7 bit even parity Hamming Code.
Answer
Sign in to view the complete answer paper.
Prove that AB′C + B + BD′+ ABD′+ A′C = B + C
Answer
Sign in to view the complete answer paper.
Simplify the following expression F = AB′+ABD+ABD′+A′C′D′+A′BC′ and implement with NAND gates.
Answer
Sign in to view the complete answer paper.
Obtain the simplified expression in SOP form and identify Prime implicants and Essential prime implicants F(A,B,C,D)= Σ m (0,1,2,3,4,8,12)
Answer
Sign in to view the complete answer paper.
Simplify the following Boolean expression using K- map and implement them with NOR logic gates F(A,B,C,D)= Σ m (1,3,7,11,15 ) + d(0,2,5)
Answer
Sign in to view the complete answer paper.
Design a combinational circuit with three input variables that will produce a logic ‘1’ output when more than one input variables are logic ‘1’?
Answer
Sign in to view the complete answer paper.
Design and explain 3 to 8 decoder with necessary truth table and logic diagram.
Answer
Sign in to view the complete answer paper.
Explain about Triggering methods in sequential circuits.
Answer
Sign in to view the complete answer paper.
Design SR flip flop using NAND gates and explain its operation.
Answer
Sign in to view the complete answer paper.
Convert D flip-flop to SR flip-flop.
Answer
Sign in to view the complete answer paper.
Derive the characteristic equation for JK flip-flop and T flip-flop.
Answer
Sign in to view the complete answer paper.
Draw the State diagram and State table for a 4 –bit Odd- Parity generator.
Answer
Sign in to view the complete answer paper.
A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produces a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed. Obtain State diagram and State table?
Answer
Sign in to view the complete answer paper.
Design a 3-bit counter which counts the following sequence 0 → 2 → 5 → 3 → 4 → 0 → 2
Answer
Sign in to view the complete answer paper.
Explain about Bi-directional Shift Register with neat logic diagram.
Answer
Sign in to view the complete answer paper.
Find the equivalence Partition and corresponding reduced state table for the given completely specified sequential machine.
Answer
Sign in to view the complete answer paper.
Draw the Merger Graph and obtain the set of maximum compatibilities for the given incompletely specified sequential machine.
Answer
Sign in to view the complete answer paper.
Draw the State diagram and ASM chart for sequence detector to detect 1010.
Answer
Sign in to view the complete answer paper.
Draw the State diagram, State table and ASM chart for a D flip-flop.
Answer
Sign in to view the complete answer paper.