JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV VLSI DESIGN Previous Question Paper (September - 2020 - R16)
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With neat sketches explain BICMOS fabrication process in a P well.
Answer
BiCMOS technology integrates Bipolar Junction Transistors (BJTs) and CMOS transistors on the same chip, combining the high input impedance and low power consumption of CMOS with the high speed and high current drive capability of bipolar devices. The fabrication of BiCMOS in a P-well process involves several critical steps to accommodate both device types on a common substrate.
The process typically starts with a P-type substrate. An N-type buried layer is formed via ion implantation in the regions where the NPN bipolar transistor will be located to reduce collector resistance. An N-epitaxial layer is then grown over the entire wafer. A deep N+ diffusion is performed to provide a low-resistance path from the collector contact to the buried layer. A P-well is then implanted and driven in to define the regions for N-channel MOSFETs.
The subsequent steps include:
- Isolation: Field oxide regions are grown using the LOCOS (Local Oxidation of Silicon) process or Shallow Trench Isolation (STI) to isolate individual devices.
- Base and Gate Formation: The base region of the NPN transistor is formed by P-type doping. Simultaneously, the gate oxide is grown, and polysilicon is deposited and patterned to form the gates of the MOSFETs and the emitter/base contacts of the BJT.
- Source/Drain and Emitter/Collector Formation: N+ and P+ implants are performed to create the source/drain regions for the MOSFETs and the emitter and collector contact regions for the NPN transistor.
- Metallization: A dielectric layer is deposited, contact holes are etched, and metal interconnects are patterned to complete the circuit.
The resulting structure features the NPN transistor within the N-epitaxial layer, while the PMOS resides in the N-epi (acting as an N-well) and the NMOS resides in the P-well. This configuration allows for the optimization of both device types, though it requires more mask steps compared to standard CMOS processes.
What is the latch up problem that arises in bulk CMOS technology? How is it overcome?
Answer
Latch-up is a failure mechanism in bulk CMOS technology caused by the formation of parasitic p-n-p-n structures within the substrate and well regions. These parasitic structures act as a silicon-controlled rectifier (SCR). When transient currents or voltage spikes trigger the base-emitter junctions of the parasitic bipolar transistors, a low-impedance path is created between the power supply (Vdd) and ground (Vss), leading to excessive current flow that can permanently damage the device.
To overcome the latch-up problem, the following design techniques are employed:
- Increasing the spacing between n-well and p-well regions to reduce the gain of the parasitic bipolar transistors.
- Using guard rings (p+ diffusion in the n-well and n+ diffusion in the p-substrate) connected to Vss and Vdd respectively to collect minority carriers before they trigger the parasitic SCR.
- Employing retrograde wells or epitaxial layers on heavily doped substrates to reduce the resistance of the substrate and well, thereby shunting the base-emitter junctions of the parasitic transistors.
- Minimizing the use of substrate contacts and ensuring low-resistance paths to the supply rails.
Explain the operation of BiCMOS inverter.
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Derive the expressions for effective resistance estimation using Elmore’s RC delay model.
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Define the principle of constant field scaling and also write its effect on device characterization.
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Construct a 4 input pseudo nMOS NAND gates.
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Classify gates and explain the GaAs growth techniques.
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Describe the special features of twin-tube process.
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Draw and explain the D.C. transfer characteristics of CMOS inverter.
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Design a stick diagram for the full adder.
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Describe in detail about memory architectures and its building blocks.
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Distinguish between PAL and PLA.
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Summarize the functions of Programmable Interconnect Points in FPGA.
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