Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech II DIGITAL LOGIC AND PULSE CIRCUITS Previous Question Paper (November/December - 2020 - R16)

B.Tech | II | II | R16 | November/December - 2020

Answer PaperPaper Code: 134ARMaximum Marks: 75Time: 2 Hours

Answer any Five Questions

All Questions Carry Equal Marks

Main

115 marks
a

i) Convert 110001.10100102 into hexadecimal and decimal.

ii) Convert (423.25)10 into Hex and binary.

8 marks

Answer

i) For binary 110001.1010010 to hexadecimal, group bits in fours from the radix point: (0011)(0001).(1010)(0010) = 31.A216. For decimal, calculate the sum of powers: 1×25 + 1×24 + 0×23 + 0×22 + 0×21 + 1×20 + 1×2-1 + 0×2-2 + 1×2-3 + 0×2-4 + 0×2-5 + 1×2-6 = 32 + 16 + 1 + 0.5 + 0.125 + 0.015625 = 49.64062510.

ii) For (423.25)10 to binary, convert integer 423: 423/2 = 211 rem 1, 211/2 = 105 rem 1, 105/2 = 52 rem 1, 52/2 = 26 rem 0, 26/2 = 13 rem 0, 13/2 = 6 rem 1, 6/2 = 3 rem 0, 3/2 = 1 rem 1, 1/2 = 0 rem 1. Binary is 110100111. Convert fractional 0.25: 0.25×2 = 0.5 (0), 0.5×2 = 1.0 (1). Binary is 110100111.012. For hexadecimal, group bits: (0001)(1010)(0111).(0100) = 1A7.416.

b

Prove that NAND and NOR are universal gates.

7 marks

Answer

A gate is universal if any Boolean function can be implemented using only that gate. NAND gates are universal because:

  1. NOT: Connect both inputs of a NAND gate together.
  2. AND: Pass the NAND output through a NOT gate (NAND followed by NAND).
  3. OR: Invert inputs using NAND gates and pass to a NAND gate (De Morgan's Law).

NOR gates are universal because:

  1. NOT: Connect both inputs of a NOR gate together.
  2. OR: Pass the NOR output through a NOT gate (NOR followed by NOR).
  3. AND: Invert inputs using NOR gates and pass to a NOR gate (De Morgan's Law).

Since AND, OR, and NOT operations can be realized, any logic circuit can be constructed using exclusively NAND or NOR gates.

215 marks
a

i) Simplify y = A(B+C)+AB+ABC.

ii) Write the truth table and symbols of AND and OR gates.

6 marks

Answer

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b

Implement XOR gate using only NAND gates and only NOR gates.

9 marks

Answer

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3

Obtain the simplified expression in sum of products for the following Boolean function.

15 marks
a

F(A,B,C,D) = ∑(2,3,12,13,14,15).

7 marks

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b

BDE+B′C′D+CDE+A′B′CE+A′B′C+B′C′D′E′

8 marks

Answer

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415 marks
a

Design full subtractor circuit.

7 marks

Answer

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b

Design a 2-bit comparator.

8 marks

Answer

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515 marks
a

Design mod-5 Asynchronous counter.

9 marks

Answer

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b

Explain the race around condition. How do you eliminate race around? Explain.

6 marks

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615 marks
a

Design a bidirectional shift register.

7 marks

Answer

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b

Derive the truth table of SR flip flop and JK flip-flop using logic diagrams.

8 marks

Answer

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7

Classify different types of clipper circuits. Draw their circuits and explain their operation.

15 marks

Answer

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815 marks
a

Derive the expression for gate width of a monostable multivibrator.

7 marks

Answer

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b

Draw and explain the transistor Miller time base generator circuit.

8 marks

Answer

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About this paper

This page contains the solved question paper with answers of DIGITAL LOGIC AND PULSE CIRCUITS from Jawaharlal Nehru Technological University Hyderabad for B.Tech EIE II II, November/December - 2020, R16.

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