Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III PULSE AND DIGITAL CIRCUITS Previous Question Paper (August - 2022 - R13)

B.Tech | III | I | R13 | August - 2022

Answer PaperPaper Code: 115EKMaximum Marks: 75Time: 3 hours

Answer any five questions. All questions carry equal marks.

Main

115 marks
a

Draw the output waveform of an RC High pass circuit with a square wave input under different time constants. Explain the same.

7 marks

Answer

An RC high-pass circuit acts as a differentiator when the time constant RC is small compared to the pulse duration, and as a simple attenuator when RC is large. For a square wave input, the output waveform depends on the ratio of the time constant to the pulse width (T/2).

1. RC >> T/2 (Large Time Constant): The capacitor charges and discharges very slowly. The output is a slightly tilted square wave, approximating the input.

2. RC = T/2: The capacitor charges significantly during the pulse duration, resulting in a noticeable exponential decay (tilt) in the output voltage.

3. RC << T/2 (Small Time Constant): The capacitor charges almost instantly. The output consists of sharp positive and negative spikes at the transitions of the input square wave, effectively differentiating the signal.

b

The square wave shown in figure 1 is fed to an RC network. What is the output? Draw the Voltage waveforms if (i) RC is very large, say RC = 10T (ii) RC is very small, say RC=T/10.

8 marks

Answer

The output of an RC circuit for a square wave input is determined by the charging and discharging behavior of the capacitor.

(i) RC = 10T (Very Large): Since the time constant is much larger than the period, the capacitor cannot charge or discharge significantly. The output voltage remains nearly constant, effectively acting as a DC-blocking circuit that preserves the shape of the square wave with minimal tilt.

(ii) RC = T/10 (Very Small): The capacitor charges and discharges rapidly within each half-cycle. The output waveform consists of a series of exponential pulses. At the rising edge of the input, the output jumps to the input voltage level and decays rapidly to zero. At the falling edge, the output jumps to a negative voltage and decays back to zero.

215 marks
a

Draw the RLC parallel circuit when step input is applied to it and explain its operation.

8 marks

Answer

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b

A symmetrical square wave whose peak to peak amplitude is A and time period is 2µ sec and whose average value zero is applied to an RC integrator circuit. The time constant is equal to half the period of square wave, find the peak to peak value of output amplitude?

7 marks

Answer

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315 marks
a

Define Clamping Circuit Theorem and explain its operation when the capacitor value is very large.

7 marks

Answer

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b

Determine Vo for the network shown in figure 2 below for the given 16V P-P sine wave input. Also sketch the transfer characteristics. (Assume ideal diodes).

8 marks

Answer

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415 marks
a

List out the few differences between clipper and clamper with examples.

5 marks

Answer

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b

Draw the shunt clipper that clips the sine wave signal above +5V and explain its working with waveforms. Also, draw its corresponding transfer characteristics.

10 marks

Answer

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515 marks
a

Define rise time, fall time, delay time and Storage time of transistor with neat diagram.

8 marks

Answer

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b

Design the Transistor switch (Inverter) for the following specifications: Vin= ±5V square wave, VCC=15V, IC=2mA, hFE=50. Assume Si transistor.

7 marks

Answer

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615 marks
a

Explain unidirectional sampling gates, with neat circuit diagram.

7 marks

Answer

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b

Explain in detail the junction diode switching times.

8 marks

Answer

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715 marks
a

Explain briefly the different methods of generating time-base waveform.

7 marks

Answer

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b

Draw the circuit diagram of Transistor Bootstrap Time Base Generator and explain its operation in detail.

8 marks

Answer

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815 marks
a

List the characteristics of TTL, RTL and CML logic families and compare them.

7 marks

Answer

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b

Draw the circuit diagram of NAND gate using TTL logic and explain.

8 marks

Answer

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This page contains the question paper of PULSE AND DIGITAL CIRCUITS from Jawaharlal Nehru Technological University Hyderabad for B.Tech EIE III I, August - 2022, R13.

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