JNTU B.Tech III MICROPROCESSORS AND COMPUTER ORGANIZATION Previous Question Paper (November/December - 2020 - R15)

The 8086 microprocessor architecture is divided into two independent functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU). This separation allows for instruction pipelining, where the BIU fetches instructions while the EU executes them, significantly increasing processing speed.

The Bus Interface Unit (BIU) handles all data and address transfers on the buses. Its components include:

• Instruction Queue: A 6-byte FIFO buffer that stores fetched instructions to implement pipelining.
• Segment Registers: Four 16-bit registers (CS, DS, SS, ES) used to address the 1MB memory space.
• Instruction Pointer (IP): Holds the offset address of the next instruction to be fetched.
• Address Adder: Generates the 20-bit physical address by combining segment and offset registers.

The Execution Unit (EU) is responsible for decoding and executing instructions. Its components include:

• General Purpose Registers: Four 16-bit registers (AX, BX, CX, DX) which can also be accessed as eight 8-bit registers.
• Pointer and Index Registers: SP, BP, SI, and DI used for memory addressing and stack operations.
• ALU: A 16-bit Arithmetic Logic Unit that performs arithmetic and logical operations.
• Flag Register: A 16-bit register containing status flags (carry, parity, auxiliary carry, zero, sign, trap, interrupt, direction, and overflow) and control flags.
• Control System: Decodes instructions from the queue and generates internal control signals.

The architecture diagram conceptually shows the BIU on the top interacting with the external system bus and the EU on the bottom. The BIU provides the instruction stream to the EU via the internal bus, while the EU provides addresses to the BIU for memory or I/O operations.