Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech II SWITCHING THEORY AND LOGIC DESIGN Previous Question Paper (November/December - 2018 - R13)

B.Tech | II | I | R13 | November/December - 2018

Answer PaperPaper Code: 113BUMaximum Marks: 75Time: 3 Hours

Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.

Part A

125 marks
a

Perform the operation 21(10) - 42(10) by using 2's complement method.

2 marks

Answer

Represent 21 as 0010101 and 42 as 00101010. To perform 21 - 42, find the 2's complement of 42 (00101010): invert bits to 11010101 and add 1 to get 11010110. Adding 00010101 and 11010110 yields 11101011. The result is negative, represented in 2's complement as -21.

b

Find the complement of F=WX+YZ then show that FF'=0 and F+F'=1.

3 marks

Answer

The complement F' = (WX + YZ)' = (WX)'(YZ)' = (W'+X')(Y'+Z'). To show FF'=0: (WX+YZ)((W'+X')(Y'+Z')) = (WX+YZ)(W'Y'+W'Z'+X'Y'+X'Z') = 0. To show F+F'=1: (WX+YZ) + (W'+X')(Y'+Z') = WX+YZ + W'Y'+W'Z'+X'Y'+X'Z' = 1 by Boolean identity expansion.

c

Simplify the Boolean function F(X,Y,Z)=Σm(0,2,4,5,6) using K-map.

2 marks

Answer

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d

Implement a Boolean function F(X,Y,Z)= Σm(2,4,6) with a multiplexer.

3 marks

Answer

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e

Explain about SR latch with NOR gates with a neat diagram.

2 marks

Answer

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f

Obtain the characteristic equation of JK Flip-flop.

3 marks

Answer

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g

Define: i) State table ii) State Diagram.

2 marks

Answer

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h

Describe a 4-bit ripple counter with a neat diagram.

3 marks

Answer

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i

Compare Mealy and Moore machines.

2 marks

Answer

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j

Describe the basic blocks of ASM chart.

3 marks

Answer

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Part B

2

Obtain 1's and 2's complements of the following binary numbers. i) 11101010 ii) 01111110 iii) 10000000 iv) 00000000. Encode the following message bits into 7-bit even parity hamming code. i) (1001)2 ii) (1110)2.

10 marks

Answer

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OR
3

Find the complement of the following functions in sum of min terms. i) F(A,B,C,D)=Σ(3,5,9,11,15) ii) F(X,Y,Z)=Π(2,4,5,7). Implement EX-NOR gate using minimum number of NAND gates.

10 marks

Answer

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4

Simplify the following boolean function using Tabular method. F(A,B,C,D)=Σm(0,1,2,5,7,8,9,10,13,15)

10 marks

Answer

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OR
5

What is the drawback of 4-bit parallel adder? And explain how to overcome the above drawback with the help of carry look ahead adder.

10 marks

Answer

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6

Explain the operation of negative edge triggered JK flip-flop with active low preset and clear inputs.

10 marks

Answer

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OR
7

Realize JK Flip-flop using SR flip-flop, D flip-flop and T flip-flop.

10 marks

Answer

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8

Design a Finite state machine which can detect a sequence of 1111 (Overlapping output) using JK Flip-flops.

10 marks

Answer

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OR
9

Describe 4-bit Universal shift register with a neat diagram.

10 marks

Answer

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10

The state table of a sequential machine is shown below. Obtain the compatibility graph using: a) Merger graph b) Merger table.

PSNS, Output
X=0 | X=1
AF,0 | A,0
BE,0 | C,0
CC, - | B,0
DF,1 | D,0
EA,1 | C,0
FD, - | F,0
10 marks

Answer

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OR
11

Design a binary multiplier and its control logic by drawing ASM chart and realize the same using decoder, MUX and D Flip-Flops.

10 marks

Answer

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This page contains the question paper of SWITCHING THEORY AND LOGIC DESIGN from Jawaharlal Nehru Technological University Hyderabad for B.Tech ETM II I, November/December - 2018, R13.

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