JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III MICROPROCESSORS AND MICROCONTROLLERS Previous Question Paper (February/March - 2022 - R16)

The 8086 microprocessor architecture is divided into two primary functional units: the Bus Interface Unit (BIU) and the Execution Unit (EU). This separation allows for pipelining, where the BIU fetches instructions while the EU executes them, significantly increasing throughput.

The Bus Interface Unit (BIU) handles all external bus operations. It contains the Instruction Stream Byte Queue (6 bytes), which stores prefetched instructions. It also manages the Segment Registers (CS, DS, SS, ES) and the Instruction Pointer (IP) to generate 20-bit physical addresses via the Address Adder.

The Execution Unit (EU) is responsible for decoding and executing instructions. It contains the Control Unit, the Arithmetic Logic Unit (ALU), and the General Purpose Registers (AX, BX, CX, DX). It also includes the Pointer and Index registers (SP, BP, SI, DI) and the 16-bit Flag Register, which tracks the status of arithmetic and logical operations.

The internal data bus connects these units, allowing the EU to receive instructions from the queue and perform operations on data fetched by the BIU.

Memory segmentation is the process of dividing the 1MB physical memory of the 8086 into logical segments, each up to 64KB in size. The significance of this approach includes:

1. Efficient Memory Management: It allows the processor to organize memory into distinct areas for code (Code Segment), data (Data Segment), stack (Stack Segment), and extra data (Extra Segment), facilitating modular programming.
2. Relocatability: Programs can be loaded into different areas of physical memory without needing to change the internal offsets, as the logical addresses are relative to the segment base.
3. Multitasking Support: By assigning different segment registers to different tasks, the processor can easily switch between multiple programs or data sets.
4. Addressing Capability: It enables the 16-bit architecture to access a 20-bit physical address space (1MB) by combining a 16-bit segment base with a 16-bit offset.