JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD MCA 2019 COMPUTER ORGANIZATION Previous Question Paper (April/May - 2019 - R15)
Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
Part A
Discuss the Combinational and Sequential Circuits.
Answer
Combinational circuits are digital circuits where the output at any instant depends only on the current input values. They have no memory elements, meaning they do not store previous states. Examples include adders, multiplexers, and decoders.
Sequential circuits are digital circuits where the output depends not only on the current inputs but also on the past sequence of inputs. These circuits incorporate memory elements (flip-flops or latches) to store state information. Examples include registers, counters, and memory units.
What is hit ratio?
Answer
Hit ratio is a performance metric used to evaluate the efficiency of a memory hierarchy, such as cache memory. It is defined as the ratio of the number of successful memory accesses (hits) to the total number of memory accesses requested by the CPU.
A higher hit ratio indicates that the cache is effectively storing the data needed by the processor, thereby reducing the frequency of slower main memory accesses.
With the help of neat diagram, explain the 8086 CPU architecture.
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What is the importance of I/O interface? In a computer system, why a PCI bus is used?
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Consider the multiplication of two 40*40 matrices using a vector processor. How many product terms are there in each inner product and how many inner products must be evaluated?
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Part B
Simplify the following Boolean function using four variables K-Map. F(A, B, C, D) = Σ(0, 1, 2, 4, 5, 7, 11, 15)
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Convert the following binary numbers to decimal: 101110; 1110101; and 110110100.
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Write the operation of 3-to-8 line decoder.
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Explain how the floating-point numbers are represented and used in digital arithmetic operations. Give an example.
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Explain the direct mapping of Cache memory?
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Give a neat sketch that illustrates the components in a typical memory hierarchy.
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How many lines of the address bus must be used to access 2048 bytes of memory? How many of these lines will be common to all chips?
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A two word instruction is stored in memory at an address designated by symbol W. The address field of the instruction (stored at W + 1) is designated by the symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by Z. An index register contains the value X. State how Z is calculated from the other addresses if the addressing mode of the instruction is (a) Direct (b) Indirect (c) Relative (d) Indexed
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Discuss the generation of physical address.
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What is meant by Addressing modes? Explain in detail.
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Compare interrupt driven data transfer scheme with DMA. Using block diagram explain interrupt driven transfer scheme.
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Why are the read and write control lines in a DMA controller bidirectional? Under what condition and for what purpose are they used as inputs? Under what condition and for what purpose are they used as outputs?
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A non-pipeline system takes 50 ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum speed up that can be achieved?
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What is a vector? Differentiate between a conventional scalar processor and a vector processor?
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List the reasons of pipeline conflicts in pipelined processor. Discuss the various conflicts that might arise in a pipeline. How are they resolved?
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