JNTU
JNTU MCA 2018 COMPUTER ORGANIZATION Previous Question Paper (June/July - 2018 - R17)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
PART - A
What is grey code? What is its importance?
Answer
Gray code is a non-weighted binary numbering system where two successive values differ in only one bit position. Its primary importance lies in minimizing errors during transitions between states in digital systems, such as in shaft encoders or Karnaugh maps, because it eliminates the problem of transient states caused by multiple bits changing simultaneously.
Briefly discuss memory hierarchy of a system.
Answer
The memory hierarchy is a pyramid-like structure organized to balance cost, capacity, and speed. At the top are registers (fastest, smallest, most expensive), followed by Cache (L1, L2, L3), Main Memory (RAM), and finally secondary storage like hard drives or SSDs (slowest, largest, cheapest). The goal is to provide the processor with fast access to frequently used data while maintaining large storage capacity at a lower cost.
Give the instruction formats of 8086 processor.
Answer
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What are the three ways that computer buses can be used to communicate with memory and I/O?
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Illustrate the vector operations carried out on vector processors.
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PART - B
Simplify the Boolean function F together with the don’t-care conditions d in a) sum of products form and b) product-of-sums form. F(w, x, y, z) = Σ (0,1,2,3,7,8,10) d(w, x, y, z) = Σ (5, 6, 11, 15)
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Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include an enable input.
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Discuss organization of a 2M × 32 memory module using 512K × 8 static memory chips with a diagram.
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A digital computer has a memory unit of 64K * 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of 4 words.
How many bits are there in the tag, index, block and word fields of the address format?
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How many bits are there in each word of cache and how are they divided into function? Include a valid bit.
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What are the various addressing modes supported by 8086? Explain them with relevant instructions.
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Write an assembly language program to check whether a given number is prime or not. Trace your program for two test cases.
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Design parallel priority interrupt hardware for a system with 8 interrupt sources.
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Explain the need of separate IO processor in a computer system and depict the communication between CPU and this processor.
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What is meant by pipelining? How does it improve the performance of a system? Explain with relevant examples.
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Discuss cache coherence problem in multi processor system and discuss any one mechanism to address this problem.
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