Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech II COMPUTER ORGANIZATION AND ARCHITECTURE Previous Question Paper (March - 2021 - R18)

B.Tech | II | I | R18 | March - 2021

Answer PaperPaper Code: 153AGMaximum Marks: 75Time: 3 hours

Answer any five questions

All questions carry equal marks

Main

115 marks
a

Discuss the functional units of a digital computer.

7 marks

Answer

A digital computer consists of five primary functional units that work together to process data:

  1. Input Unit: Accepts raw data and instructions from external sources (e.g., keyboard, mouse) and converts them into a machine-readable binary format.
  2. Memory Unit: Stores programs and data. It is divided into primary memory (RAM/ROM) for fast access by the CPU and secondary storage (HDD/SSD) for long-term data retention.
  3. Arithmetic Logic Unit (ALU): Performs all arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations required for data processing.
  4. Control Unit (CU): Acts as the central nervous system of the computer. It coordinates the activities of all other units by issuing control signals, managing instruction execution, and controlling data flow.
  5. Output Unit: Converts processed binary results into human-readable form (e.g., monitors, printers).
b

Demonstrate construction of a common bus system with multiplexers.

8 marks

Answer

A common bus system allows multiple registers to transfer data to a single shared path using multiplexers to select which register's output is placed on the bus at any given time. For a system with n registers of k bits each, the construction involves:

  1. Multiplexer Selection: Use k multiplexers, where each multiplexer has n inputs. Each input corresponds to the same bit position across all n registers.
  2. Control Lines: The selection lines of all k multiplexers are tied together. A set of log2(n) control lines is used to select which register will output its data to the bus.
  3. Data Routing: If register R0 is selected, the 0th input of every multiplexer is routed to its respective output, effectively placing the contents of R0 onto the bus lines.
  4. Bus Width: The number of multiplexers used equals the word size (k bits), ensuring that all bits of the selected register are transferred in parallel.

This configuration prevents bus contention by ensuring only one register's output is enabled on the bus lines simultaneously.

215 marks
a

Design a 4-bit combinational circuit decrementer using four full-adder circuits.

7 marks

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b

What is the difference between a direct and an indirect address instruction? How many references to memory are needed for each type of instruction to bring an operand into a processor register?

8 marks

Answer

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315 marks
a

Discuss the need of memory stack and stack limits.

7 marks

Answer

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b

Explain the general register organization of the processor.

8 marks

Answer

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4

Explain addition and subtraction of floating point numbers with an example and necessary flowchart.

15 marks

Answer

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515 marks
a

A two way set associative cache has lines of 16 bytes and a total size of 8 K bytes. The 64 Mbytes main memory is byte addressable. Show the format of main memory address.

8 marks

Answer

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b

How does SDRAM differ from ordinary DRAM?

7 marks

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615 marks
a

Explain the major differences between the central computer and peripheral. How to resolve these differences?

8 marks

Answer

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b

Discuss the Strobe control method of Asynchronous data transfer.

7 marks

Answer

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715 marks
a

What is parallel processing? Explain Flynn’s classification of computer.

8 marks

Answer

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b

Illustrate vector operations and vector processing.

7 marks

Answer

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815 marks
a

Discuss about RISC Pipeline.

7 marks

Answer

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b

What is cache coherence problem? Discuss solutions for it.

8 marks

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About this paper

This page contains the question paper of COMPUTER ORGANIZATION AND ARCHITECTURE from Jawaharlal Nehru Technological University Hyderabad for B.Tech CSE II I, March - 2021, R18.

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