JNTU B.Tech II COMPUTER ORGANIZATION AND ARCHITECTURE Previous Question Paper (October - 2020 - R18)

A bus system for four registers (R0, R1, R2, R3) is constructed using multiplexers to select the output of one register to be placed onto the common bus. Each register is n-bits wide, and the system requires four n-line multiplexers, each with four inputs.

The selection is controlled by two selection lines (S1, S0) connected to the select inputs of all multiplexers. When S1S0 = 00, the output of R0 is selected; for 01, R1 is selected; for 10, R2 is selected; and for 11, R3 is selected. The common bus receives the n-bit output from the selected multiplexer, allowing data transfer to other registers or functional units without requiring direct point-to-point connections between every pair of registers, thereby significantly reducing the number of wires in the system.

Given the initial 8-bit register value: 10011100.

Arithmetic Shift Right (ASR): The sign bit (MSB) is preserved, and all bits are shifted one position to the right. The MSB remains 1, and the new value becomes 11001110.

Arithmetic Shift Left (ASL): All bits are shifted one position to the left, and a 0 is inserted into the LSB. The initial value 10011100 becomes 00111000.

Overflow Check: An overflow occurs in an arithmetic shift left if the bit shifted out of the MSB position (the sign bit) differs from the bit that was originally in the MSB position. Here, the original MSB was 1, and the bit shifted out was 1. Since the sign bit did not change (it remains 0 in the new MSB, but the transition from 1 to 0 indicates a change in the sign bit's value), an overflow has occurred because the magnitude has exceeded the capacity of the signed representation.