Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III ADVANCED COMPUTER ARCHITECTURE Previous Question Paper (March - 2021 - R18)

B.Tech | III | I | R18 | March - 2021

Answer PaperPaper Code: 155AAMaximum Marks: 75Time: 3 Hours

Answer any five questions. All questions carry equal marks.

Main

115 marks
a

Discuss the evolution of computer architecture.

5 marks

Answer

The evolution of computer architecture is characterized by a transition from monolithic, single-processor systems to highly parallel, distributed, and specialized computing environments. This progression can be categorized into several distinct generations:

  • First Generation (Vacuum Tubes): Based on vacuum tubes, these machines were physically massive, consumed significant power, and relied on machine language programming.
  • Second Generation (Transistors): The introduction of transistors replaced vacuum tubes, leading to smaller, more reliable, and faster systems. This era saw the emergence of high-level languages like FORTRAN and COBOL.
  • Third Generation (Integrated Circuits): The development of ICs allowed for the miniaturization of components, leading to the birth of minicomputers and the concept of multiprogramming.
  • Fourth Generation (VLSI): The advent of Very Large Scale Integration enabled the creation of microprocessors, leading to the personal computer revolution.
  • Fifth Generation (Parallelism and AI): Modern architecture focuses on multi-core processors, massive parallelism, heterogeneous computing (CPUs + GPUs/TPUs), and cloud-based distributed architectures to overcome the limitations of sequential processing (the memory wall and power wall).
b

Differentiate between implicit parallelism and explicit parallelism.

5 marks

Answer

Parallelism refers to the ability of a system to perform multiple operations simultaneously. The distinction between implicit and explicit parallelism is defined by the responsibility for identifying and managing concurrent tasks:

  • Implicit Parallelism: In this model, the hardware or the compiler is responsible for detecting and exploiting parallelism without explicit instructions from the programmer. The compiler analyzes data dependencies and reorders instructions to utilize multiple functional units. Examples include superscalar processors and out-of-order execution engines.
  • Explicit Parallelism: Here, the programmer or the language construct explicitly defines which parts of the code can run in parallel. This requires the use of specific parallel programming models or APIs (such as OpenMP, MPI, or CUDA). The programmer is responsible for managing synchronization, data partitioning, and communication between threads or processes.
Implicit = Hardware/Compiler-driven; Explicit = Programmer-driven
c

Describe NUMA model for shared memory multiprocessor.

5 marks

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215 marks
a

Give the Bell’s taxonomy of MIMD computers.

5 marks

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b

Describe an operational model of an SIMD computer.

5 marks

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c

Define the five types of data dependence.

5 marks

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315 marks
a

Make a comparison of Amdahl’s law and Gustafson’s law as speed up performance models.

8 marks

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b

Identify the basic metrics affecting the scalability of a computer system for a given application.

7 marks

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415 marks
a

Distinguish between RISC and CISC scalar processors.

8 marks

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b

Describe the architecture of a typical VLIW processor and instruction format.

7 marks

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515 marks
a

What is meant by bus arbitration? Explain Daisy-chain bus arbitration.

7 marks

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b

Describe Total Store Order weak consistency model used in SPARC architecture.

8 marks

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615 marks
a

What is the importance of dynamic instruction scheduling? Explain Tomasulo’s algorithm.

8 marks

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b

Illustrate the schematic design of a cross point switch in a crossbar network.

7 marks

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715 marks
a

Explain the building blocks and the application paradigms of the Connection Machine (CM) -5.

7 marks

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b

Discuss the routing schemes followed in a multi computer network and analyze their communication latencies.

8 marks

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815 marks
a

Describe any two latency hiding techniques for enhancing scalability and programmability.

8 marks

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b

Explain the message-driven processor architecture.

7 marks

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