JNTU
JNTU B.Tech III COMPUTER ORGANIZATION Previous Question Paper (August - 2022 - R16)
Answer any five questions. All questions carry equal marks.
Main
Draw the flowchart for instruction cycle and give the micro operations corresponding to fetch and decode.
Answer
The instruction cycle is the sequence of steps a CPU performs to execute an instruction. It consists of two main phases: the Fetch cycle and the Execute cycle. The instruction cycle begins by fetching an instruction from memory, decoding it, and then executing it.
The flowchart starts with the Start state, followed by the Fetch cycle. During Fetch, the Program Counter (PC) value is placed on the address bus to access the instruction. Once fetched, the instruction is decoded to determine the operation to be performed. If the instruction requires memory access, the Effective Address (EA) is calculated. Finally, the instruction is executed, and the cycle repeats for the next instruction.
The micro-operations for the Fetch cycle are:
The micro-operations for the Decode cycle are:
In these steps, MAR represents the Memory Address Register, PC is the Program Counter, MBR is the Memory Buffer Register, and IR is the Instruction Register. The timing signals T0, T1, T2, and T3 synchronize the execution of these micro-operations within the processor control unit.
Explain about address sequencing in microprogrammed control unit.
Answer
Address sequencing in a microprogrammed control unit refers to the method used to determine the address of the next microinstruction to be executed. The control unit must be capable of sequencing through microinstructions in the control memory to perform the required operations. The next address is determined by the Next Address Generator (also called a microprogram sequencer) based on the following sources:
- Incrementing: The simplest method is to increment the current control address register (CAR) by 1 to point to the next sequential microinstruction.
- Unconditional Branching: The address field of the current microinstruction is loaded into the CAR, allowing a jump to any location in the control memory.
- Conditional Branching: The next address is selected based on status bits from the processor (e.g., zero flag, carry flag). If the condition is met, the address field of the microinstruction is loaded; otherwise, the CAR is incremented.
- Subroutine Calls: A microprogram can call a sub-microprogram. The return address is saved in a stack, and the CAR is loaded with the starting address of the subroutine.
- Mapping: When a new instruction is fetched from the main memory, the opcode is mapped to a starting address in the control memory using a mapping logic circuit.
Explain the block diagram of digital computer.
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Explain the following addressing modes with examples:
Register addressing mode
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Indexed addressing mode
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Intrasegment addressing modes
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Explain about Assembler directives and operations.
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Explain about 8086 processor architecture.
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Write an ALP to find whether the given number is a palindrome or not.
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Explain how to pass the parameters to procedures with an example.
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Write an ALP to find the factorial of a given number.
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Explain the stack structure of 8086.
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Draw the flow chart for Booth Multiplication and multiply -15 with 7 using Booth Multiplication Algorithm.
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How data is transferred between I/O devices without involving the processor? Explain.
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Discuss the challenges occurred in instruction pipelining.
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Explain about the Associate memory.
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