JNTU
JNTU B.Tech IV SYSTEM DESIGN USING FPGAS Previous Question Paper (July - 2023 - R16)
Note: i) Question paper consists of Part A, Part B.
ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.
Part A
Explain about synthesis Technology library.
Answer
A synthesis technology library is a collection of logical cells (such as AND, OR, NOT gates, flip-flops, and multiplexers) specific to a target semiconductor manufacturing process or FPGA architecture. It provides the synthesis tool with critical information including timing delays, area consumption, power characteristics, and physical constraints for each primitive cell, enabling the tool to map high-level RTL code into an optimized gate-level netlist.
Write the HDL Synthesis Rules in detail.
Answer
HDL synthesis rules are guidelines that ensure RTL code is effectively translated into hardware:
- Completeness: All signals must be assigned values in all possible branches of conditional statements (if-else, case) to prevent the inference of unwanted latches.
- Sensitivity Lists: For combinational logic, all input signals must be included in the sensitivity list; for sequential logic, only the clock and asynchronous reset/preset signals should be present.
- Resource Sharing: Synthesis tools attempt to share hardware resources like arithmetic units (adders, multipliers) across multiple operations to minimize area.
- Blocking vs Non-blocking: Use blocking assignments for combinational logic and non-blocking assignments for sequential logic to avoid simulation-synthesis mismatches.
Discuss about Barrel Shifter in short.
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Write a VHDL program for 2-bit comparator.
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What is control register?
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Explain about Interrupt Registers.
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Define clock skew.
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Explain about Race around conditions.
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Write a short note on gated clock.
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Explain about Design verification.
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Part B
What is meant by HDL? Compare this with the other High-level languages.
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Explain JK flipflop implementation from VHDL code.
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Discuss the design of four, two input NAND gate using VHDL statement, also obtain the synthesized schematic for NAND gate.
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Draw and explain the 2-4 synthesized schematic for flipflop.
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What is code converter? Explain about its working principle.
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Draw and write a VHDL Program for carry ripple adder.
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Draw and explain about synthesized schematic for SELECTOR RTL2.
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Draw and Write a VHDL program for full adder.
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Draw and explain synthesized schematic diagram of parallel to serial converter.
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Explain schematic diagram of shift register and draw the simulation waveform.
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Explain about Register Block portioning in detail.
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Write a VHDL code for JK flip flop.
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Explain about Clock domain and Clock divider.
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Explain about Reset circuitry and its advantages.
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Implement the design of divided-by-3 clock divider circuit using VHDL coding.
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Explain about Clock buffer and clock tree.
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Why post layout verification is needed?
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How Net list will be generated? Explain.
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Explain about Worst-case Timing Analysis.
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Explain about Design management and Design synthesis.
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