JNTU B.Tech IV SYSTEM DESIGN USING FPGAS Previous Question Paper (July/August - 2022 - R16)

HDL synthesis rules are a set of coding guidelines and constraints that ensure hardware description language code can be effectively mapped into physical logic gates and flip-flops. These rules bridge the gap between behavioral descriptions and structural implementation.

Key synthesis rules include:

• Sensitivity Lists: In Verilog, combinational logic must include all input signals in the sensitivity list. Missing signals lead to inferred latches rather than pure combinational logic.
• Blocking vs. Non-blocking Assignments: Use blocking assignments (=) for combinational logic and non-blocking assignments (<=) for sequential logic to prevent race conditions and ensure correct hardware timing.
• Complete Conditional Statements: All if-else and case statements must cover all possible input combinations. Incomplete specifications result in the synthesis tool inferring unintended latches to hold state.
• Reset Logic: Sequential elements should ideally include an asynchronous or synchronous reset to ensure a known initial state upon power-up.
• Resource Sharing: Synthesis tools attempt to share operators like adders or multipliers across different parts of the code to minimize area, provided the timing constraints allow it.

The significance of these rules lies in ensuring design portability, predictable hardware behavior, and area-power-timing optimization. Adhering to these rules prevents the creation of 'inferred latches' which are often undesirable in synchronous designs, and ensures that the simulation behavior matches the actual post-synthesis gate-level implementation.

A synthesis technology library is a database provided by the FPGA or ASIC vendor that contains the physical and electrical characteristics of the available hardware primitives (cells) in the target device. It serves as the reference point for the synthesis tool during the mapping phase.

The library typically includes:

• Cell Definitions: Descriptions of basic logic gates (AND, OR, NOT), flip-flops, multiplexers, and complex macro-cells like DSP slices or Block RAMs.
• Timing Models: Detailed information regarding propagation delays, setup/hold times, and clock-to-output delays for each cell.
• Area/Power Metrics: Data on the physical footprint and power consumption characteristics of each primitive.

During synthesis, the tool translates the generic RTL code into a netlist by selecting the most suitable components from this library to satisfy the user's constraints regarding speed, area, and power.