JNTU
JNTU B.Tech IV SYSTEM DESIGN USING FPGAS Previous Question Paper (September - 2022 - R16)
Answer any five questions. All questions carry equal marks.
Main
Describe the integrated VHDL/Verilog design process and methodology with a neat flow chart.
Answer
The integrated design process for FPGAs involves a structured flow from high-level specification to physical device configuration. The methodology typically follows these stages:
- Design Specification: Defining the system requirements and functional behavior.
- HDL Coding: Writing the design using VHDL or Verilog.
- Simulation (RTL): Verifying the functional correctness of the code using testbenches.
- Synthesis: Converting the HDL code into a netlist of logic gates and flip-flops mapped to FPGA primitives.
- Place and Route (Implementation): Mapping the netlist to specific physical resources (CLBs, routing matrices) on the FPGA.
- Static Timing Analysis: Ensuring the design meets setup and hold time constraints.
- Bitstream Generation: Creating the configuration file for the FPGA.
- Device Programming: Downloading the bitstream into the FPGA hardware.
The flow chart proceeds linearly from Specification to HDL Coding, followed by a verification loop between Simulation and Coding. Post-synthesis, the flow moves through Implementation, Timing Analysis, and Bitstream Generation, concluding with Hardware Testing.
Write a functional behavioral model for bi-directional pad, three state output pad and pull down three-state output pad.
Answer
Functional behavioral models for I/O pads are implemented using tri-state logic buffers. In Verilog, the inout port is used for bi-directional signals, while output is used for tri-state pads.
1. Bi-directional Pad:
module bi_dir_pad(inout pad, input data_in, input oe, output data_out);
assign pad = (oe) ? data_in : 1'bz;
assign data_out = pad;
endmodule2. Three-state Output Pad:
module tri_state_pad(output pad, input data, input oe);
assign pad = (oe) ? data : 1'bz;
endmodule3. Pull-down Three-state Output Pad:
module pull_down_tri_state(output pad, input data, input oe);
// Using a weak pull-down resistor equivalent
tri (weak0, weak1) pad_internal = 1'b0;
assign pad = (oe) ? data : 1'bz;
assign pad = pad_internal;
endmoduleDraw a different schematic to use D-flip flop and other combinational circuit gates that can be used to implement a JK flip-flop.
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Define a design directory structure for a design by two or more designers. State the assumptions, guidelines, usages, advantages and purposes.
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What is a Selector? Write the VHDL/Verilog code for selection of any one of the inputs identified from the 16-bit inputs and selected by using a 4-bit identifier input.
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Synthesize VHDL/Verilog code for all architectures with N => 32. Compare the synthesis results.
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The COUNTONE circuit can be implemented with array of full adders in the same way to add a column bits at a certain bit position for multiplier design. Each column of full adders will generate a sum bit. The carry bits from a column of full adders will be passed to the next column of full adders. Develop VHDL/Verilog code to capture this design concept.
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What is a Barrel Shifter? Develop a VHDL/Verilog code to do an arithmetic shift right Barrel Shifter, assuming 2’s complement with the left most bit as the sign bit.
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What is a Signal Extender? Develop a VHDL/Verilog code for Signal Extender.
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Use a carry look ahead concept to develop a synchronous counter that runs faster with a smaller clock period. Synthesize the VHDL/Verilog code.
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What are the different interrupt registers? Write a VHDL/Verilog code showing how these different interrupt registers can control the interrupt. Also draw the synthesized schematic for the code.
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What are configuration registers? Develop a VHDL/Verilog code for to implement configuration registers and the multiplexer circuit.
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What is meant by Clock Skew? Discuss the Timing Violations caused due to Clock Skew and also develop a VHDL/Verilog code to fix the timing violation along with necessary diagrams.
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Draw the synthesized schematic for Clock divider along with simulation waveform. Also develop a VHDL/Verilog code that divides the Clock to get a slower speed clock.
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Develop a VHDL/Verilog code for the design of an FIR filter with six FIR ASICs.
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Describe in detail about Post Layout Verification.
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