JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III COMPUTER ARCHITECTURE Previous Question Paper (February - 2022 - R18)

B.Tech | III | I | R18 | February - 2022

Answer PaperPaper Code: 155AKMaximum Marks: 75Time: 3 hours

Answer any five questions. All questions carry equal marks.

Main

115 marks
a

Differentiate between CISC and RISC architectures. Discuss their characteristics.

8 marks

Answer

CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) represent two distinct design philosophies in computer architecture:

FeatureCISCRISC
Instruction SetLarge, complex, variable-length instructionsSmall, simple, fixed-length instructions
Instruction ExecutionMulti-cycle executionSingle-cycle execution
Memory AccessMemory-to-memory operations supportedLoad/Store architecture (only load/store access memory)
RegistersFew general-purpose registersLarge number of general-purpose registers
Control UnitMicroprogrammedHardwired
PipeliningDifficult to implementHighly efficient

CISC aims to reduce the number of instructions per program by providing complex instructions that perform multiple operations, whereas RISC focuses on simplifying instructions to increase the clock speed and optimize pipeline performance.

b

Explain the operation of Control Unit.

7 marks

Answer

The Control Unit (CU) acts as the 'brain' of the CPU, directing the flow of data and instructions between the processor and other components. Its operation follows a systematic cycle:

  1. Instruction Fetch: The CU retrieves the next instruction from memory using the Program Counter (PC) and stores it in the Instruction Register (IR).
  2. Instruction Decode: The CU interprets the opcode in the IR to determine the required operation and identifies the necessary operands.
  3. Effective Address Calculation: If the instruction involves memory access, the CU calculates the address of the data.
  4. Operand Fetch: The CU triggers the necessary control signals to fetch data from memory or registers.
  5. Execution: The CU sends specific control signals to the Arithmetic Logic Unit (ALU) or other functional units to perform the operation.
  6. Write Back: The CU manages the storage of the result back into a register or memory location.

The CU operates either via hardwired logic (using combinational circuits for high speed) or microprogramming (using a control memory to store microinstructions for flexibility).

215 marks
a

Explain any five arithmetic micro operations.

7 marks

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b

Describe the multi-bus organization with a neat sketch.

8 marks

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315 marks
a

What is Virtual memory? Discuss the issues involved in implementing virtual memory.

7 marks

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b

Explain the functions of DMA controller.

8 marks

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415 marks
a

Define Cache memory and describe about features of self-associative and direct mapping.

7 marks

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b

What are the features of PCI Express Bus? Explain.

8 marks

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515 marks
a

Differentiate between IA-32 and IA-64.

7 marks

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b

What is segmentation? How it is done in 8086? Explain.

8 marks

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615 marks
a

Explain about Concurrent operation of EU and BIU.

8 marks

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b

Discuss about the instruction set of 8086 in brief.

7 marks

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715 marks
a

What is Pipelining? Explain about Instruction level pipelining (ILP).

8 marks

Answer

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b

Discuss about the compiler techniques for ILP.

7 marks

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815 marks
a

With a neat sketch, explain the DSP architecture.

7 marks

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b

Discuss in brief about MIPS processor and its programming.

8 marks

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About this paper

This page contains the question paper of COMPUTER ARCHITECTURE from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech EEE III I, February - 2022, R18.

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