JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III COMPUTER ARCHITECTURE Previous Question Paper (March - 2021 - R18)

The fundamental distinction between RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) lies in the philosophy of instruction design and hardware implementation.

• Instruction Set Complexity: RISC utilizes a small, highly optimized set of simple instructions that execute in a single clock cycle. CISC employs a large, complex instruction set where a single instruction can perform multiple low-level operations (e.g., load, arithmetic, store).
• Hardware vs. Software: RISC emphasizes software-based complexity, relying on compilers to optimize code, whereas CISC implements complex operations directly in hardware via microcode.
• Instruction Length: RISC instructions are typically of fixed length (e.g., 32-bit), facilitating efficient pipelining. CISC instructions are of variable length, which complicates instruction decoding.
• Memory Access: RISC follows a Load-Store Architecture, where memory access is restricted to specific load and store instructions. CISC allows arithmetic operations to be performed directly on memory operands.
• Register Usage: RISC architectures feature a large number of general-purpose registers to minimize memory traffic. CISC architectures typically have fewer registers and rely more heavily on memory.
• Pipelining: RISC is designed specifically to support efficient instruction pipelining. CISC is harder to pipeline due to the varying complexity and execution times of instructions.

The Load Register operation is a fundamental instruction in load-store architectures used to transfer data from a specific memory address into a CPU register. The process involves the following sequential steps:

1. Instruction Fetch (IF): The control unit fetches the load instruction from the program memory using the address stored in the Program Counter (PC).
2. Instruction Decode (ID): The CPU decodes the instruction to identify the operation (Load), the target register (e.g., R1), and the memory address calculation method (e.g., base register + offset).
3. Effective Address Calculation (EX): The processor calculates the target memory address. If an offset is provided, the CPU adds the immediate value to the contents of the base register.
Effective Address = Base Register + Offset
4. Memory Access (MEM): The CPU places the calculated address on the Address Bus and sends a read signal to the memory controller. The memory unit retrieves the data stored at that location and places it on the Data Bus.
5. Write Back (WB): The data from the Data Bus is latched into the specified destination register within the CPU, and the PC is updated to point to the next instruction.