JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III IC APPLICATIONS Previous Question Paper (August/September - 2024 - R13)

B.Tech | III | I | R13 | August/September - 2024

Answer PaperPaper Code: 115AHMaximum Marks: 75Time: 3 hours

Note: i) Question paper consists of Part A, Part B.
ii) Part A is compulsory, which carries 25 marks. In Part A, Answer all questions.
iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions.

Part A

125 marks
a

Why inductors are difficult to fabricate as an ICs?

2 marks

Answer

Inductors are difficult to fabricate on an IC because they require large surface areas for high inductance values and suffer from low quality factors (Q) due to the high series resistance of thin-film metal traces. Furthermore, they cannot be easily integrated using standard planar semiconductor manufacturing processes.

b

Classify the ICs based on the application, device and chip complexity.

3 marks

Answer

ICs are classified as follows:

  • Application: Linear (Analog) ICs and Digital ICs.
  • Device: Monolithic ICs and Hybrid (Thin/Thick film) ICs.
  • Chip Complexity: Small Scale Integration (SSI), Medium Scale Integration (MSI), Large Scale Integration (LSI), Very Large Scale Integration (VLSI), and Ultra Large Scale Integration (ULSI).
c

List the characteristics of ideal op-amp.

2 marks

Answer

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d

How input offset voltage is compensated?

3 marks

Answer

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e

What are the advantages of active filters?

2 marks

Answer

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f

State two conditions of oscillator and why these are needed?

3 marks

Answer

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g

Define lock range in PLL.

2 marks

Answer

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h

What is VCO? With reference to this, define voltage to frequency conversion factor.

3 marks

Answer

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i

Which one is fastest ADC? State the reason.

2 marks

Answer

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j

What output would be produced by a 2-bit D/A converter whose output range is 0 to 10V and whose input binary number is 10.

3 marks

Answer

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Part B

2

What is the advantage of open collector output in TTL and explain the working of standard TTL NAND gate functionality with neat circuit diagram.

10 marks

Answer

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OR
310 marks
a

How TTL gate drive the CMOS gate?

4 marks

Answer

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b

What is tristate TTL? Explain its working with neat diagrams.

6 marks

Answer

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410 marks
a

Explain the general stages of op-amp with neat block diagram.

6 marks

Answer

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b

Explain the terms CMRR and slew rate of op-amp.

4 marks

Answer

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OR
510 marks
a

Draw and explain the circuit of voltage to current converter.

5 marks

Answer

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b

What are the different features of 741 op amp?

5 marks

Answer

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6

Design a second order active low pass filter and derive the equation for its transfer function and also draw its frequency response.

10 marks

Answer

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OR
7

Design a wien bridge oscillator using op-amp, to oscillate at 100Hz and draw its circuit diagram.

10 marks

Answer

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810 marks
a

Draw the pin diagram of 555 timer and write its applications.

5 marks

Answer

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b

In the Astable multivibrator of 555 timer RA=6.6kΩ, RB=3.3kΩ and C=0.1μF. Calculate tH, tL free running frequency and duty cycle.

5 marks

Answer

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OR
9

Draw the block diagram of PLL and explain the function of each block.

10 marks

Answer

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10

Explain Inverted R-2R ladder DAC with suitable circuit diagram and discuss its advantages and disadvantages.

10 marks

Answer

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OR
11

Explain how dual slope ADC is used to convert analog input to digital output with neat circuit diagram and compare its performance with other ADCs.

10 marks

Answer

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About this paper

This page contains the solved question paper with answers of IC APPLICATIONS from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech EEE III I, August/September - 2024, R13.

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