Jawaharlal Nehru Technological University Hyderabad
Jawaharlal Nehru Technological University Hyderabad B.Tech III Year IC APPLICATIONS Previous Question Paper (August - 2022 - R13)
Answer any five questions. All questions carry equal marks.
Main
Compare the TTL and CMOS logic families.
Answer
| Feature | TTL (Transistor-Transistor Logic) | CMOS (Complementary Metal Oxide Semiconductor) |
|---|---|---|
| Basic Element | Bipolar Junction Transistors (BJT) | MOSFETs |
| Power Dissipation | High (increases with frequency) | Very low (mostly at switching) |
| Propagation Delay | Low (fast) | Higher than TTL |
| Noise Margin | Moderate | Excellent (high) |
| Fan-out | Typically 10 | Very high (typically 50+) |
| Input Impedance | Low | Very high |
| Supply Voltage | Fixed (typically 5V) | Wide range (typically 3V to 18V) |
Design a TTL 2-state NAND gate and explain its operation.
Answer
A standard TTL 2-input NAND gate consists of four main stages: the input stage (multi-emitter transistor), the phase splitter, and the totem-pole output stage. The input stage uses a multi-emitter BJT where the emitters serve as inputs A and B.
- When both inputs are at logic HIGH (5V), the base-collector junction of the input transistor is forward-biased, allowing current to flow into the base of the phase-splitter transistor.
- The phase-splitter transistor turns ON, which in turn drives the lower transistor of the totem-pole output stage into saturation, pulling the output to a logic LOW state.
- If either or both inputs are at logic LOW (0V), the input transistor's base-emitter junction is forward-biased, diverting current away from the phase-splitter.
- The phase-splitter turns OFF, causing the upper transistor of the totem-pole output to conduct and the lower transistor to cut off, pulling the output to a logic HIGH state.
This configuration ensures that the output is only LOW when both inputs are HIGH, satisfying the NAND logic function.
Explain the operation TTL open collector gate.
Answer
Sign in to view the complete answer paper.
What is interfacing? Explain the operation of TTL driving CMOS.
Answer
Sign in to view the complete answer paper.
Explain the operation of instrumentation amplifier. What are the features of it? Write any three applications of it.
Answer
Sign in to view the complete answer paper.
The input signal Vi of an op amp is 0.04 sin 1.13×105t is to be amplified to the maximum extent. How much maximum gain can be had by using op amp with a slew rate of 0.4V/sec?
Answer
Sign in to view the complete answer paper.
Explain and draw the output waveforms of the ideal integrator circuit when the input is i) sine wave ii) square wave and iii) step input.
Answer
Sign in to view the complete answer paper.
Draw the differential amplifier circuit using op-amp and explain its working.
Answer
Sign in to view the complete answer paper.
Design a second order High pass active filter with cutoff frequency of 2 kHz and also draw its frequency response.
Answer
Sign in to view the complete answer paper.
Explain the operation of all pass filter and draw its circuit diagram.
Answer
Sign in to view the complete answer paper.
Explain how the oscillations are generated in RC wein bridge oscillator.
Answer
Sign in to view the complete answer paper.
Design a op amp circuit which can give the output as V0 = 2V1 - 3V2 + 4V3 - 5V4.
Answer
Sign in to view the complete answer paper.
Derive the Lock range and capture range in PLL and explain their significance in the working of PLL.
Answer
Sign in to view the complete answer paper.
Explain the PLL as a FM detector.
Answer
Sign in to view the complete answer paper.
Draw the IC 1408 DAC pin diagram and explain.
Answer
Sign in to view the complete answer paper.
What is the role of DAC in successive approximation ADC?
Answer
Sign in to view the complete answer paper.