Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III IC APPLICATIONS Previous Question Paper (July/August - 2023 - R13)

B.Tech | III | I | R13 | July/August - 2023

Answer PaperPaper Code: 115AHMaximum Marks: 75Time: 3 hours

Answer any five questions. Part A is compulsory. Answer any one question from each unit of Part B.

Part A

125 marks
a
Define “fan-in” and “fan-out”. Which one are you likely to have to calculate? Why?
2 marks

Answer

Fan-in is the number of inputs a gate can handle, while fan-out is the maximum number of standard logic inputs a gate output can drive without violating specifications. You must calculate fan-out because it determines the loading capability and signal integrity of the circuit design.
b
Which would you expect to be faster, a TTL AND gate or a TTL AND-OR-INVERT gate? Why?
3 marks

Answer

A TTL AND gate is faster. The AND-OR-INVERT (AOI) gate involves more internal transistor stages and logic levels, which increases the cumulative propagation delay compared to a simple AND gate.
c
Define Slew rate.
2 marks

Answer

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d
What causes the slew rate? And how is it measured?
3 marks

Answer

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e
What is an all pass filter? Where and why is it needed?
2 marks

Answer

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f
What is VCO? Explain why it is called a Voltage-to-Frequency convertor?
3 marks

Answer

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g
Define Duty cycle. What is its significance?
2 marks

Answer

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h
How PLLs are used as frequency multipliers, dividers and demodulators?
3 marks

Answer

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i
Why is an inverted R-2R ladder network DAC better than R-2R ladder DAC?
2 marks

Answer

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j
How many levels are possible in a 3-bit DAC? What is its resolution if the output range is 0-5V?
3 marks

Answer

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Part B

210 marks
a
Draw 2-input CMOS NOR gate and then explain the same.
5 marks

Answer

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b
Explain the classification and applications of different integrated circuits.
5 marks

Answer

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OR
310 marks
a
Explain the operation of CMOS driving TTL.
5 marks

Answer

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b
Compare all the logic families.
5 marks

Answer

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410 marks
a
What are the ideal characteristics of the operational amplifier and how do they differ practically.
5 marks

Answer

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b
Explain the effects of time on input-offset voltage and input-offset current.
5 marks

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OR
510 marks
a
Draw high frequency model of an op-amp and explain its working.
5 marks

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b
Draw and explain the operation of an op-amp as an integrator.
5 marks

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610 marks
a
Design a first order low pass filter at a cutoff frequency of 2KHz with a pass band gain of 2 and plot the frequency response.
6 marks

Answer

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b
Explain how the frequency scaling is accomplished in an active filter.
4 marks

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OR
710 marks
a
Design a quadrature oscillator to operate at a frequency of 1.5KHz.
5 marks

Answer

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b
Explain the steps to compute the quality factor of a wide band reject filter circuit.
5 marks

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810 marks
a
With neat circuit diagrams, explain the Astable mode of operation of 555 timer.
5 marks

Answer

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b
In the 555 monostable multivibrator circuit, if RA=10KΩ. Determine the value of C for output pulse duration of 1ms.
5 marks

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OR
910 marks
a
Design a 555 astable multivibrator to operate at 10KHz with 40% duty cycle.
5 marks

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b
Explain the operation of the PLL with the help of the block diagram.
5 marks

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1010 marks
a
Compare R-2R and weighted resistor types of DACs.
4 marks

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b
Explain the operation of inverted R-2R ladder type DAC with the help of neat diagram.
6 marks

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OR
1110 marks
a
Explain how to perform analog to digital conversion using dual slope ADC.
6 marks

Answer

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b
What are the merits and demerits of parallel comparator type ADC? Explain.
4 marks

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This page contains the solved question paper with answers of IC APPLICATIONS from Jawaharlal Nehru Technological University Hyderabad for B.Tech EEE III I, July/August - 2023, R13.

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