JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech III IC APPLICATIONS Previous Question Paper (November/December - 2017 - R13)

B.Tech | III | I | R13 | November/December - 2017

Answer PaperPaper Code: 115AHMaximum Marks: 75Time: 3 hours

Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.

Part A

125 marks
a

Realize EX-OR gate with CMOS circuit.

2 marks

Answer

An EX-OR gate can be realized using CMOS technology by combining a transmission gate-based structure or by using a combination of NAND and NOR gates. A common CMOS implementation uses 12 transistors to achieve the logic function Y = A ⊕ B = A'B + AB'.

b

Mention the reasons why open loop is not preferred for linear applications.

3 marks

Answer

Open-loop configuration is not preferred for linear applications because: 1) The open-loop gain is extremely high, making the output prone to saturation even with tiny input signals. 2) The gain is highly sensitive to temperature and power supply variations. 3) The output is highly unstable due to the lack of feedback control.

c

List out the ideal characteristics of op-amp.

2 marks

Answer

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d

Write the features of 741 op-amp.

3 marks

Answer

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e

Mention the differences between band pass and Band Reject filter.

2 marks

Answer

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f

Mention the blocks present in IC565.

3 marks

Answer

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g

What are the modes of operation of a Timer?

2 marks

Answer

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h

List various applications of IC 555 Timer.

3 marks

Answer

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i

Explain how Dual-slope ADC provides noise rejection?

2 marks

Answer

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j

Compare R-2R and Weight Resistor types of ADC.

3 marks

Answer

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Part B

210 marks
a

Design a TTL 2-state NAND gate and explain its operation.

5 marks

Answer

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b

Draw the resistive model of a CMOS inverter and explain its behaviour for LOW and HIGH outputs.

5 marks

Answer

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OR
310 marks
a

Classify IC s and write about the Chip size.

5 marks

Answer

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b

Explain about the TTL driving CMOS gate.

5 marks

Answer

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410 marks
a

Derive input resistance for inverting amplifier with feedback arrangement.

5 marks

Answer

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b

What is the operation performed by an inverting Op-Amp amplifier if its feedback resistance is replaced by a capacitance? Explain the functioning of such circuit. What are the practical difficulties associated with this circuit?

5 marks

Answer

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OR
510 marks
a

An IC op-amp 741 used as an inverting amplifier with a gain of 100. The voltage gain vs frequency characteristic is flat up to 12 kHz. Find the maximum peak to peak input signal that can be feed without causing any distortion to the output.

5 marks

Answer

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b

Explain the operation of V to I converter.

5 marks

Answer

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610 marks
a

Derive the expression for the transfer function of first order high pass filter.

5 marks

Answer

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b

Draw the schematic diagram of Wein bridge oscillator and explain its working.

5 marks

Answer

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OR
710 marks
a

Explain the operation of VCO.

5 marks

Answer

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b

Discuss about the operation of Wein Bridge Oscillator.

5 marks

Answer

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810 marks
a

Describe the functional block diagram of 555 timer.

5 marks

Answer

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b

How 555 timer can be used in Schmitt Trigger circuit.

5 marks

Answer

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OR
910 marks
a

With a neat diagram explain the operation of PLL.

5 marks

Answer

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b

Write about the applications of PLL.

5 marks

Answer

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1010 marks
a

Explain the operation of Successive approximation ADC.

5 marks

Answer

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b

Write about the ADC specifications.

5 marks

Answer

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OR
1110 marks
a

Discuss about the binary weighted resistor DAC.

5 marks

Answer

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b

Mention the applications of DAC and ADC.

5 marks

Answer

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About this paper

This page contains the solved question paper with answers of IC APPLICATIONS from JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD for B.Tech EEE III I, November/December - 2017, R13.

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