Jawaharlal Nehru Technological University Hyderabad

Jawaharlal Nehru Technological University Hyderabad B.Tech III IC APPLICATIONS Previous Question Paper (November/December - 2018 - R13)

B.Tech | III | I | R13 | November/December - 2018

Answer PaperPaper Code: 115AHMaximum Marks: 75Time: 3 hours

Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.

PART - A

125 marks
a

Define Monolithic and Hybrid IC Technologies.

2 marks

Answer

Monolithic IC: All circuit components (active and passive) and their interconnections are formed on a single semiconductor chip. Hybrid IC: Passive components and interconnections are formed on an insulating substrate, while active components are attached as separate chips or devices.

b

What are the advantages of ICs over discrete circuits?

3 marks

Answer

Advantages include: 1) Extremely small size and low weight. 2) Higher reliability due to the absence of soldered joints. 3) Lower power consumption and cost due to mass production. 4) Improved performance and faster operating speeds.

c

Define Input and Output Offset-voltages.

2 marks

Answer

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d

Compare Open loop and Closed loop configurations of Op-Amp.

3 marks

Answer

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e

What is the use of VCO?

2 marks

Answer

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f

Compare 1st order Low Pass and High Pass filters.

3 marks

Answer

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g

Draw the block diagram for PLL.

2 marks

Answer

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h

Distinguish between Astable and Monostable Multi-vibrators.

3 marks

Answer

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i

Which is the fastest ADC and why?

2 marks

Answer

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j

For a particular 8-bit ADC, the conversion time is 9 µs. Find the maximum frequency of an input sine wave that can be digitized.

3 marks

Answer

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PART - B

210 marks
a

Draw 2-input TTL NAND gate and explain its operation with the help of functional table.

5 marks

Answer

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b

Draw the CMOS transmission gate and realize a 2×1 MUX using this transmission gate.

5 marks

Answer

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OR
310 marks
a

Draw the CMOS circuit diagram of Tri-State Buffer? Explain the circuit with the help of logic diagram and function table.

5 marks

Answer

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b

What is the necessity of separate interfacing circuit to connect CMOS gate to TTL gate? Draw the interface circuit and explain the operation?

5 marks

Answer

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4

Draw the circuit and explain the operation of Instrumentation Amplifier. Derive the expression for its output voltage.

10 marks

Answer

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OR
510 marks
a

An Op-Amp has a differential gain of 80 dB and CMRR of 95 dB. If V1=2 µV and V2 = 1.6 µV, then calculate differential and common mode output values.

5 marks

Answer

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b

Explain the principle of operation of Sample and Hold circuit.

5 marks

Answer

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6

Draw the basic circuit of RC - Phase Shift Oscillator and explain its operation. Also derive the expression for frequency of Oscillation.

10 marks

Answer

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OR
710 marks
a

Design first order high pass filter with a cut off frequency of 10 KHz with a pass band gain of 1.5.

5 marks

Answer

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b

Explain various types of filters along with their frequency response.

5 marks

Answer

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810 marks
a

Derive the expression for the Duty cycle of an Astable Multi-vibrator using IC555.

6 marks

Answer

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b

Compare and contrast Schmitt trigger and Comparator.

4 marks

Answer

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OR
910 marks
a

Derive an expression for Capture Range of PLL.

5 marks

Answer

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b

Show that the Lock-in Range of a PLL is given by ΔfL= ±7.8fo/V, Where the symbols used have the usual meaning.

5 marks

Answer

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1010 marks
a

Find the Resolution of 12-bit D/A Converter.

5 marks

Answer

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b

An 8-bit Successive Approximation ADC is driven by a 1 MHz clock. Find its Conversion time.

5 marks

Answer

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OR
1110 marks
a

Obtain an expression for the output voltage of R-2R DAC.

5 marks

Answer

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b

Explain how Dual Slope A/D converter provides Noise rejection.

5 marks

Answer

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This page contains the solved question paper with answers of IC APPLICATIONS from Jawaharlal Nehru Technological University Hyderabad for B.Tech EEE III I, November/December - 2018, R13.

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