JNTU
JNTU B.Tech IV VLSI DESIGN Previous Question Paper (December-2023/January-2024 - R15)
Note: i) Question paper consists of Part A, Part B. ii) Part A is compulsory, which carries 25 marks. In Part A, answer all questions. iii) In Part B, Answer any one question from each unit. Each question carries 10 marks and may have a, b as sub questions
Part A
What is pull down and pull up device?
Answer
A pull-down device is typically an nMOS transistor connected between the output node and ground, designed to pull the output voltage to logic low. A pull-up device is a transistor (or load) connected between the output node and the supply voltage (Vdd), designed to pull the output voltage to logic high.
List the basic process for IC fabrication.
Answer
- Silicon wafer preparation.
- Epitaxial growth.
- Oxidation.
- Photolithography.
- Diffusion or Ion implantation.
- Metallization and Interconnection.
What is stick diagram?
Answer
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Give the different scaling models and scaling factors?
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What is meant by standard unit of capacitance?
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List the constraints in choice of layers.
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Define the term counter.
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Write about general considerations in subsystem design processes.
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What is the need for testing?
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List out the applications of FPGAs.
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Part B
With neat sketches explain the CMOS n-well fabrication process indicating the masks used.
Answer
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Derive an equation for ID of an n-channel Enhancement MOSFET operating in the saturation region and non-saturation region.
Answer
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Illustrate the lambda-based design rules with neat sketches.
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Draw the symbolic layout for the CMOS inverter and write the general CMOS logic gate layout guidelines.
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What are the alternate gate circuits available? Explain any one of the items with a suitable sketch.
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Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit.
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Describe the nature of a parity generator and explain its structured design approach.
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Draw the basic circuit diagram of static RAM and explain its read and write operations.
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Explain the various design strategies for test.
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What are the drawbacks of PLAs? How PLAs are used to implement combinational and sequential logic circuits? Give one example.
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