JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD B.Tech IV VLSI DESIGN Previous Question Paper (November/December - 2018 - R15)
Note: This question paper contains two parts A and B. Part A is compulsory which carries 25 marks. Answer all questions in Part A. Part B consists of 5 Units. Answer any one full question from each unit. Each question carries 10 marks and may have a, b, c as sub questions.
PART A
What are enhancement mode device?
Answer
An enhancement mode device is a transistor that is normally in the OFF state when the gate-to-source voltage is zero. It requires a threshold voltage (Vt) greater than zero to be applied to the gate to form a conducting channel between the source and drain.
Write the important advantages of CMOS inverter over than others inverter configurations.
Answer
The CMOS inverter offers several advantages over other configurations:
- Near-zero static power dissipation because one transistor is always OFF in steady state.
- High noise immunity due to a rail-to-rail output voltage swing.
- Excellent scalability and high packing density, making it ideal for VLSI integration.
Define the term scaling.
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What is the necessity of design rules?
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What do you meant by inverter delay?
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Write the advantages of cascading dynamic logic gates.
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Define full adder.
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Compare and contrast the RAM and ROM.
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What are the different stuck at faults?
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Compare and contrasts the CPLD and FPGA.
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PART B
Explain the fabrications of NMOS with corresponding neat sketches.
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Describe the briefly diffusion of circuit elements.
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Illustrate the importance of figure of merit in MOS device.
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Discuss the analysis of NMOS inverter with corresponding block diagram.
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Describe the transistor design rules in NMOS lambda based design rules with suitable diagrams.
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Define the stick diagram and draw the neat stick layout diagram of CMOS inverter.
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Explain the double metal MOS process rules.
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Derive the scaling factor of device parameters power dissipation per unit area and switching energy per gate.
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With suitable examples describe briefly complex logic gates in CMOS.
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Estimate the inverter delays for rise time and fall time of CMOS.
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Describe briefly the concept of driving large capacitive loads.
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Explain the significant source of wiring capacitances in detailed.
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Explain the monolithic look ahead adder with the block diagram.
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Explain the operation of 4 bit zero/ one detector with corresponding block diagram.
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Draw a transistor-level circuit diagram for a three-input DRAM core cell and explain the principle operation of it.
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Compare and contrast SRAM and DRAM.
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With suitable example, Realize NOR NMOS PLA.
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Explain the XILINK programmable gate array with example.
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Discuss the need of CMOS testing.
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How does implemented the serial scan test? Explain.
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